公开(公告)号：US07723226B2

公开(公告)日：2010-05-25

申请号：US11654427

申请日：2007-01-17

Applicant: Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

Inventor： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

Abstract translation: 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

公开(公告)号：US20100065969A1

公开(公告)日：2010-03-18

申请号：US12591532

申请日：2009-11-23

Applicant: Chen-Hua Yu ,  Shwang-Ming Jeng ,  Yung-Cheng Lu ,  Huilin Chang ,  Ting-Yu Shen ,  Yichi Liao

Inventor： Chen-Hua Yu ,  Shwang-Ming Jeng ,  Yung-Cheng Lu ,  Huilin Chang ,  Ting-Yu Shen ,  Yichi Liao

IPC: H01L23/532 ,  H01L23/48

CPC classification number: B29C43/222 ,  A44B17/0029 ,  A44B17/0058 ,  B29C43/28 ,  B29C2793/009 ,  B29L2031/7282 ,  B29L2031/729 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/45099

Abstract: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.

Abstract translation: 提供了至少具有用于半导体器件的接合焊盘的集成电路器件及其制造方法。 接合焊盘具有具有多个开口的第一钝化层。 覆盖在开口和第一钝化层的部分上的导电层，其具有覆盖第一钝化层的第一部分和覆盖开口的第二部分。 第二钝化层覆盖在第一钝化层上并覆盖导电层的边缘。

公开(公告)号：US07629273B2

公开(公告)日：2009-12-08

申请号：US11523674

申请日：2006-09-19

Applicant: Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

Inventor： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/3105 ,  H01L21/823807 ,  H01L29/7843

Abstract: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.

Abstract translation: 一种形成半导体结构的方法包括提供包括第一器件区域的衬底，在第一器件区域中形成金属氧化物半导体（MOS）器件，在MOS器件上形成应力层，并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线（UV）固化，激光固化，电子束固化及其组合组成的组。

公开(公告)号：US07619368B2

公开(公告)日：2009-11-17

申请号：US11175349

申请日：2005-07-05

Applicant: Chao-Cheng Lu

Inventor： Chao-Cheng Lu

IPC: H05B39/04 ,  H05B37/00

CPC classification number: H05B41/2824 ,  Y02B20/186

Abstract: A power source apparatus is disclosed in this invention, specifically a power source apparatus comprising a voltage amplitude control unit that employs an active power factor corrector to control the output DC voltage by applying positive or negative logic control voltage, incorporated with high frequency power source circuit and high frequency transformer, brightness of Cold Cathode Fluorescent Lamp (CCFL) or External Electrode Fluorescent Lamp (EEFL) are controllable and DC power is directly applied to DC load. Such method is accomplished by adjusting the amplitude of the supplying DC voltage for controlling the amplitude of the high frequency voltage of CCFL or EEFL, thus called Voltage Amplitude Method. Because of the characteristics of stable frequency, high resolution and linearity, VAM is broadly used in the control of luminance of discharge tubes, such as TFT-LCD TVs, LCD monitors and advertisement lamps. The impulse width controller of the present invention achieves the luminance control of CCFL or EEFL inside or outside the glow discharge zone.

Abstract translation: 在本发明中公开了一种电源装置，具体地说是一种电源装置，包括电压幅度控制单元，该电压幅度控制单元采用有源功率因数校正器，通过施加正或负的逻辑控制电压来控制输出直流电压，其中包括高频电源电路 和高频变压器，冷阴极荧光灯（CCFL）或外部电极荧光灯（EEFL）的亮度是可控的，直流电源直接用于直流负载。 这种方法是通过调节供电直流电压的幅度来实现的，以控制CCFL或EEFL的高频电压的振幅，因此称为电压幅度法。 由于稳定的频率，高分辨率和线性度的特点，VAM广泛应用于TFT-LCD电视机，液晶显示器和广告灯等放电管的亮度控制。 本发明的脉冲宽度控制器实现辉光放电区域内部或外部的CCFL或EEFL的亮度控制。

公开(公告)号：US20090275195A1

公开(公告)日：2009-11-05

申请号：US12500796

申请日：2009-07-10

Applicant: Chen-Hua Yu ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Hung Chun Tsai

Inventor： Chen-Hua Yu ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Hung Chun Tsai

IPC: H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.

Abstract translation: 提供集成电路的互连结构及其形成方法。 互连结构包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的导体和导体上的覆盖层。 盖层至少具有包含金属硅化物/锗化物的顶部。

公开(公告)号：US20090257276A1

公开(公告)日：2009-10-15

申请号：US12192137

申请日：2008-08-15

Applicant: Cheng-Da Huang ,  Chih-Cheng Lu ,  Hsin Chen

Inventor： Cheng-Da Huang ,  Chih-Cheng Lu ,  Hsin Chen

IPC: G11C27/00 ,  G11C16/06 ,  G11C7/00

CPC classification number: G11C27/005 ,  G11C16/0441

Abstract: A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a first current source, a second current source, and a current adjuster. The first current source generates a first current, and the second current source generates a second current. The current adjuster turns on or turns off a current path of the second current according to a reference current and the first current. Furthermore, when the current path of the second current is turned on, the first current is adjusted according to the second current, such that the first current is equal to the reference current.

Abstract translation: 非易失性模拟存储器具有浮动栅极点。 非易失性模拟存储器包括第一电流源，第二电流源和电流调节器。 第一电流源产生第一电流，第二电流源产生第二电流。 电流调节器根据参考电流和第一电流打开或关闭第二电流的电流路径。 此外，当第二电流的电流路径导通时，根据第二电流来调节第一电流，使得第一电流等于参考电流。

公开(公告)号：US20090160394A1

公开(公告)日：2009-06-25

申请号：US12128806

申请日：2008-05-29

Applicant: Yu Zhang ,  Cheng Lu ,  Jian-Ping Ying

Inventor： Yu Zhang ,  Cheng Lu ,  Jian-Ping Ying

IPC: H02P21/14

CPC classification number: H02P21/14

Abstract: A control apparatus for an induction motor is provided and includes a rotating-speed locked loop and a feed-forward magnetizing-axis angular position emulator. The rotating-speed locked loop emulates a speed control loop of the induction motor for producing an emulated torque current and an emulated rotor angular speed. The feed-forward magnetizing-axis angular position emulator receives the emulated torque current and the emulated rotor angular speed for producing a feed-forward estimated magnetizing-axis angular position, wherein according to the feed-forward estimated magnetizing-axis angular position, a first voltage controlling the induction motor is transformed from a synchronous reference coordinate system of the induction motor to a static reference coordinate system of the induction motor, and a two-phase current detected from the induction motor is transformed from the static reference coordinate system to the synchronous reference coordinate system. The state the stator angular frequency is at zero can be skipped through the apparatus.

Abstract translation: 提供一种用于感应电动机的控制装置，包括旋转速度锁定环和前馈磁化轴角位置仿真器。 旋转速度锁定环模拟感应电动机的速度控制回路，用于产生仿真转矩电流和仿真转子角速度。 前馈磁化轴角位置仿真器接收仿真转矩电流和仿真转子角速度，用于产生前馈估计磁化轴角位置，其中根据前馈估计磁化轴角位置，第一 将感应电动机的电压控制从感应电动机的同步参考坐标系变换为感应电动机的静态参考坐标系，将从感应电动机检测到的两相电流从静态参考坐标系变换为同步 参考坐标系。 定子角频率为零的状态可以通过该装置跳过。

公开(公告)号：US07486568B2

公开(公告)日：2009-02-03

申请号：US11742398

申请日：2007-04-30

Applicant: Yi Ying Liao ,  Chih Chieh Yeh ,  Wen Jer Tsai ,  Tao Cheng Lu

Inventor： Yi Ying Liao ,  Chih Chieh Yeh ,  Wen Jer Tsai ,  Tao Cheng Lu

IPC: G11C11/34

CPC classification number: G11C16/3404

Abstract: Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge, in the erased state than i.n the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.

Abstract translation: 电荷捕获存储器单元被保护以响应于擦除命令而被过擦除。 例如，响应于擦除命令，将一个偏置装置应用于编程电荷俘获存储器单元，并且施加另一个偏置布置以擦除电荷捕获存储器单元，使得电荷捕获存储器单元具有较高的净电荷， 处于擦除状态，而不是编程状态。 在另一示例中，具有电荷俘获存储器单元阵列的集成电路具有通过向电荷捕获存储器单元施加相似的偏置布置来响应擦除命令的逻辑。 在另一实例中，制造这种集成电路。

公开(公告)号：US07486086B2

公开(公告)日：2009-02-03

申请号：US11979576

申请日：2007-11-06

Applicant: Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

Inventor： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

IPC: G01R27/26

CPC classification number: G01R31/2621

Abstract: A method for measuring intrinsic capacitance of a MOS device is provided. The MOS device includes a first terminal, a second terminal, a third terminal and a fourth terminal. First, provide a first input signal to the second terminal and ground the third terminal and fourth terminal. Then, charge the first terminal and measure a first current required for charging the first terminal. Afterward, provide a second input signal to the second terminal, ground the third terminal and the fourth terminal, and measure a second current required for charging the first terminal, wherein the first input signal and the second input signal have the same low level, but different high levels. Finally, determine intrinsic capacitance between the first terminal and the second terminal according to the first current, the second current and a high level difference between the first input signal and the second input signal.

Abstract translation: 提供了一种用于测量MOS器件的本征电容的方法。 MOS器件包括第一端子，第二端子，第三端子和第四端子。 首先，向第二终端提供第一输入信号，并将第三终端和第四终端接地。 然后，对第一终端充电并测量对第一终端充电所需的第一电流。 然后，向第二终端提供第二输入信号，将第三端子和第四端子接地，并测量对第一端子充电所需的第二电流，其中第一输入信号和第二输入信号具有相同的低电平，但是 不同的高层次。 最后，根据第一电流，第二电流和第一输入信号与第二输入信号之间的高电平差来确定第一端子和第二端子之间的本征电容。

公开(公告)号：US07446047B2

公开(公告)日：2008-11-04

申请号：US11061350

申请日：2005-02-18

Applicant: Minghsing Tsai ,  Yung-Cheng Lu

Inventor： Minghsing Tsai ,  Yung-Cheng Lu

IPC: H01L21/311

CPC classification number: H01L21/76834 ,  H01L21/02118 ,  H01L21/0226 ,  H01L21/3127 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835

Abstract: A passivated metal structure and a method of forming the metal structure is disclosed. According to one embodiment, the patterned metal structure, such as conductive lines, are formed on a substrate. The copper lines are passivated by a polymer liner between the copper lines and a low k dielectric filling the spaces between the conductive lines. The polymer liner is preferably deposited on the sidewalls of the conductive lines by electro-grafting. The polymer liner may also be used in a damascene process according to a second embodiment.

Abstract translation: 公开了钝化金属结构和形成金属结构的方法。 根据一个实施例，图案化的金属结构，例如导电线，形成在基板上。 铜线由铜线之间的聚合物衬垫和填充导电线之间的空间的低k电介质钝化。 聚合物衬垫优选通过电接枝沉积在导电线的侧壁上。 聚合物衬垫也可以用于根据第二实施例的镶嵌工艺中。