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    Methods of fabricating light emitting diode packages
    32.
    发明授权
    Methods of fabricating light emitting diode packages 有权
    制造发光二极管封装的方法

    公开(公告)号：US08241932B1

    公开(公告)日：2012-08-14

    申请号：US13050549

    申请日：2011-03-17

    Applicant: Chih-Kuang Yu ,  Chyi Shyuan Chern ,  Hsing-Kuo Hsia ,  Hung-Yi Kuo

    Inventor： Chih-Kuang Yu ,  Chyi Shyuan Chern ,  Hsing-Kuo Hsia ,  Hung-Yi Kuo

    IPC: H01L21/00

    CPC classification number: H01L25/0753 ,  H01L24/24 ,  H01L24/82 ,  H01L33/0079 ,  H01L33/44 ,  H01L33/62 ,  H01L2224/73267 ,  H01L2924/01029 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2933/0033 ,  H01L2924/00

    Abstract: An LED array comprises a growth substrate and at least two separated LED dies grown over the growth substrate. Each of LED dies sequentially comprise a first conductive type doped layer, a multiple quantum well layer and a second conductive type doped layer. The LED array is bonded to a carrier substrate. Each of separated LED dies on the LED array is simultaneously bonded to the carrier substrate. The second conductive type doped layer of each of separated LED dies is proximate to the carrier substrate. The first conductive type doped layer of each of LED dies is exposed. A patterned isolation layer is formed over each of LED dies and the carrier substrate. Conductive interconnects are formed over the patterned isolation layer to electrically connect the at least separated LED dies and each of LED dies to the carrier substrate.

    Abstract translation: LED阵列包括生长衬底和在生长衬底上生长的至少两个分离的LED管芯。 每个LED管芯依次包括第一导电型掺杂层，多量子阱层和第二导电型掺杂层。 LED阵列结合到载体衬底。 LED阵列上的每个分离的LED管芯同时结合到载体衬底。 每个分离的LED管芯的第二导电型掺杂层靠近载体衬底。 每个LED管芯的第一导电型掺杂层被暴露。 在每个LED管芯和载体衬底上形成图案化隔离层。 导电互连形成在图案化的隔离层上，以将至少分离的LED管芯和每个LED管芯电连接到载体衬底。

    DEVICE WITH ALUMINUM SURFACE PROTECTION
    33.
    发明申请
    DEVICE WITH ALUMINUM SURFACE PROTECTION 有权
    具有铝表面保护的器件

    公开(公告)号：US20120086075A1

    公开(公告)日：2012-04-12

    申请号：US13327992

    申请日：2011-12-16

    Applicant: Kuo Bin HUANG ,  Ssu-Yi LI ,  Ryan Chia-Jen CHEN ,  Chi-Ming YANG ,  Chyi Shyuan CHERN ,  Chin-Hsiang LIN

    Inventor： Kuo Bin HUANG ,  Ssu-Yi LI ,  Ryan Chia-Jen CHEN ,  Chi-Ming YANG ,  Chyi Shyuan CHERN ,  Chin-Hsiang LIN

    IPC: H01L27/088

    CPC classification number: H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer.

    Abstract translation: 具有金属栅极结构的半导体结构包括具有第一栅极的第一型场效应晶体管，包括：基板上的高k电介质材料，高k电介质材料层上的第一金属层，具有第一功函数，以及 在第一金属层上的第一铝层。 第一铝层包括包含铝，氮和氧的界面层。 该器件还包括具有第二栅极的第二类场效应晶体管，其包括：衬底上的高k电介质材料，高k电介质材料层上的第二金属层，具有不同于第一功函数的第二功函数， 和在第二金属层上的第二铝层。

    Integration of bottom-up metal film deposition
    35.
    发明授权
    Integration of bottom-up metal film deposition 有权
    整合自下而上的金属膜沉积

    公开(公告)号：US08088685B2

    公开(公告)日：2012-01-03

    申请号：US12702525

    申请日：2010-02-09

    Applicant: Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

    Inventor： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

    IPC: H01L21/4763

    CPC classification number: H01L29/78 ,  C23C14/022 ,  C23C14/046 ,  C23C14/18 ,  C23C14/221 ,  C23C16/0263 ,  C23C16/045 ,  C23C16/06 ,  C23C16/48 ,  C23C16/484 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76877 ,  H01L29/4966 ,  H01L29/66545

    Abstract: The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios.

    Abstract translation: 自下而上金属沉积以填充互连和替代栅极结构的方法的所述实施例使得能够在没有空隙的情况下间隙填充具有高纵横比的精细特征，并提供具有良好膜质量的金属膜。 通过气体簇离子束（GCIB）沉积的金属膜的原位预处理允许去除表面杂质和表面氧化物以改善下层与沉积的金属膜之间的粘附。 通过使用高能量的低频光源在较低温度下通过光致化学气相沉积（PI-CVD）沉积的金属膜表现出液体性质，这允许金属膜从下向上填充精细特征。 通过PI-CVD沉积的金属膜的后沉积退火致密化金属膜并从金属膜去除残留的气态物质。 对于先进的制造，这种自下而上的金属沉积方法解决了具有高纵横比的精细特征的间隙填充的挑战。

    Formation of Shallow Trench Isolation Using Chemical Vapor Etch
    37.
    发明申请
    Formation of Shallow Trench Isolation Using Chemical Vapor Etch 有权
    使用化学蒸气蚀刻法形成浅沟槽隔离

    公开(公告)号：US20100267172A1

    公开(公告)日：2010-10-21

    申请号：US12426711

    申请日：2009-04-20

    Applicant: Ying XIAO ,  Chyi Shyuan CHERN

    Inventor： Ying XIAO ,  Chyi Shyuan CHERN

    IPC: H01L21/66 ,  C23F1/08

    CPC classification number: H01L22/20 ,  H01L21/76224 ,  H01L22/12

    Abstract: A method includes measuring a depth of a shallow trench isolation (STI) region below a surface of a substrate. The STI region is filled with an oxide material. The substrate has a nitride layer above the surface. A thickness of the nitride layer is measured. A first chemical vapor etch (CVE) of the oxide material is performed, to partially form a recess in the STI region. The first CVE removes an amount of the oxide material less than the thickness of the nitride layer. The nitride layer is removed by dry etching. A remaining height of the STI region is measured after removing the nitride. A second CVE of the oxide material in the STI region is performed, based on the measured depth and the remaining height, to form at least one fin having a desired fin height above the oxide in the STI region without an oxide fence.

    Abstract translation: 一种方法包括测量衬底表面下面的浅沟槽隔离（STI）区域的深度。 STI区域填充有氧化物材料。 衬底在表面上方具有氮化物层。 测量氮化物层的厚度。 执行氧化物材料的第一化学气相蚀刻（CVE），以在STI区域中部分地形成凹陷。 第一CVE去除少于氮化物层的厚度的一定量的氧化物材料。 通过干蚀刻去除氮化物层。 在去除氮化物之后测量STI区的剩余高度。 基于测量的深度和剩余高度，执行STI区域中的氧化物材料的第二CVE，以形成在没有氧化物栅栏的STI区域中具有高于氧化物的所需翅片高度的至少一个翅片。

    METHOD AND SYSTEM FOR CONTROLLING AN IMPLANTATION PROCESS
    38.
    发明申请
    METHOD AND SYSTEM FOR CONTROLLING AN IMPLANTATION PROCESS 有权
    用于控制植入过程的方法和系统

    公开(公告)号：US20100221849A1

    公开(公告)日：2010-09-02

    申请号：US12394201

    申请日：2009-02-27

    Applicant: Nai-Han Cheng ,  Chyi Shyuan Chern

    Inventor： Nai-Han Cheng ,  Chyi Shyuan Chern

    IPC: H01L21/66 ,  B05C11/00

    CPC classification number: H01L21/26513 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for implant uniformity is provided that includes determining a variation of critical dimensions (CD) of a semiconductor wafer, moving the semiconductor wafer in a two-dimensional mode during an implantation process, and controlling a velocity of the movement of the semiconductor wafer so that an implant dose to the semiconductor wafer is varied based on the variation of CD.

    Abstract translation: 提供了一种用于植入均匀性的方法，其包括确定半导体晶片的临界尺寸（CD）的变化，在注入过程期间以二维模式移动半导体晶片，以及控制半导体晶片的移动速度 基于CD的变化改变对半导体晶片的植入剂量的变化。

    N/P metal crystal orientation for high-K metal gate Vt modulation
    39.
    发明授权
    N/P metal crystal orientation for high-K metal gate Vt modulation 有权
    N / P金属晶体取向用于高K金属栅Vt调制

    公开(公告)号：US08674451B2

    公开(公告)日：2014-03-18

    申请号：US12332057

    申请日：2008-12-10

    Applicant: Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Chin-Hsiang Lin

    Inventor： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Chin-Hsiang Lin

    IPC: H01L21/70

    CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/4958

    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.

    Abstract translation: 本发明提供集成电路。 集成电路包括具有第一区域和第二区域的半导体衬底; 在所述第一区域中的n型场效应晶体管（FET）的第一栅极堆叠; 以及第二区域中的p型FET的第二栅极堆叠。 第一栅极堆叠包括在半导体衬底上的高k电介质层，在高k电介质层上具有第一取向的第一晶体金属层和第一晶体金属层上的导电材料层。 第二栅极堆叠包括半导体衬底上的高k电介质层，在高k电介质层上具有第二取向的第二晶体金属层和第二晶体金属层上的导电材料层。

    Method for fabricating an isolation structure
    40.
    发明授权
    Method for fabricating an isolation structure 有权
    隔离结构的制造方法

    公开(公告)号：US08580653B2

    公开(公告)日：2013-11-12

    申请号：US13775907

    申请日：2013-02-25

    Applicant: Tze-Liang Lee ,  Pei-Ren Jeng ,  Chu-Yun Fu ,  Chyi Shyuan Chern ,  Jui-Hei Huang ,  Chih-Tang Peng ,  Hao-Ming Lien

    Inventor： Tze-Liang Lee ,  Pei-Ren Jeng ,  Chu-Yun Fu ,  Chyi Shyuan Chern ,  Jui-Hei Huang ,  Chih-Tang Peng ,  Hao-Ming Lien

    IPC: H01L21/76

    CPC classification number: H01L21/76224 ,  H01L21/76232

    Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.

    Abstract translation: 一种制造隔离结构的方法，包括在衬底的顶表面中形成沟槽并用第一氧化物部分地填充沟槽，其中第一氧化物是纯氧化物。 部分地填充沟槽包括在沟槽中形成衬层，并且在低于10毫托（mTorr）的压力和约500℃至约1000℃的温度下使用硅烷和氧前体在衬层上形成第一氧化物 该方法还包括在第一氧化物的顶部产生固体反应产物。 该方法还包括通过在室内在100℃至200℃的温度下加热基底来升华固体反应产物，并通过使载气流过基底而除去升华的固体反应产物。 该方法还包括用第二氧化物填充沟槽。

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