公开(公告)号：US20140068203A1

公开(公告)日：2014-03-06

申请号：US14013275

申请日：2013-08-29

申请人： JONG PIL SON ,  CHUL WOO PARK ,  HAK SOO YU ,  HONG SUN HWANG

发明人： JONG PIL SON ,  CHUL WOO PARK ,  HAK SOO YU ,  HONG SUN HWANG

IPC分类号： G06F3/06

CPC分类号： G06F3/061 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0676 ,  G06F3/068 ,  G06F13/1642 ,  G11C7/00 ,  G11C7/1048 ,  G11C11/4076 ,  Y02D10/14

摘要： A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

摘要翻译： 存储器系统包括存储器件和存储器控制器。 存储装置包括多个存储单元。 存储器控制器被配置为在活动命令和预充电命令之间在存储器设备上连续地执行多个写入命令。 在存储器系统中，当执行了具有多个写入命令的最后写入命令的第一次写入操作之后，然后执行预充电命令时，在预充电命令之后发出最后一个写入命令用于第二次写入操作。 第一写入操作和第二写入操作将相同的数据写入具有相同地址的多个存储单元的存储单元。

公开(公告)号：US08477554B2

公开(公告)日：2013-07-02

申请号：US13152316

申请日：2011-06-03

申请人： Hak-soo Yu ,  In-gyu Baek ,  Hong-sun Hwang ,  Young-kug Moon

发明人： Hak-soo Yu ,  In-gyu Baek ,  Hong-sun Hwang ,  Young-kug Moon

IPC分类号： G11C5/14 ,  G11C5/02 ,  G11C5/06

CPC分类号： G11C5/063 ,  G11C5/025

摘要： A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers.

摘要翻译： 一种半导体存储器件，包括多个层，每个层包括存储单元阵列并彼此堆叠; 以及用于向层供电的至少一个电力平面。 电力平面包括施加电源电压的区域和施加接地电压的区域。 施加电源电压的区域位于与施加接地电压的区域相邻的位置处，并且在其间形成去耦电容器，以将功率噪声涌入到层中或在层中产生功率噪声。

公开(公告)号：US20080165559A1

公开(公告)日：2008-07-10

申请号：US12006502

申请日：2008-01-03

申请人： Nam-Seog Kim ,  Hak-Soo Yu ,  Uk-Rae Cho

发明人： Nam-Seog Kim ,  Hak-Soo Yu ,  Uk-Rae Cho

IPC分类号： G11C5/06 ,  G11C7/10

CPC分类号： G11C5/063 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18 ,  G11C11/417

摘要： A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.

摘要翻译： 数据线布局结构包括多个第一数据线，第二数据线，第三数据线，第一数据线驱动器和第二数据线驱动器。 多个第一数据线连接到存储器垫中的子垫，使得预定数量的第一数据线连接到每个子垫。 第二数据线的布置量比第一数据线的数量少，从而形成相对于第一数据线的层次。 第三数据线被布置成相对于第二数据线形成层级，并且将通过第二数据线提供的数据传送到数据锁存器。 第一数据线驱动器连接在第一数据线和第二数据线之间，并且执行用于输出第一数据线的逻辑“或”运算，以驱动对应的第二数据线。 第二数据线驱动器连接在第二数据线和第三数据线之间，并且执行用于输出第二数据线的逻辑“或”运算，以驱动第三数据线。

公开(公告)号：US20070115710A1

公开(公告)日：2007-05-24

申请号：US11480447

申请日：2006-07-05

申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

IPC分类号： G11C5/06

CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

公开(公告)号：US6166969A

公开(公告)日：2000-12-26

申请号：US345582

申请日：1999-06-30

申请人： Byoung-Cheol Song ,  Hak-Soo Yu ,  Kwang-Jin Lee

发明人： Byoung-Cheol Song ,  Hak-Soo Yu ,  Kwang-Jin Lee

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/34 ,  H03K19/0185 ,  G11C7/00

CPC分类号： G11C7/06 ,  H03K19/018521

摘要： Disclosed is a level shifter that can receive and convert a first signal that can have various voltage logic levels to a second signal having internal voltage logic levels. The level shifter includes first and second ascending/descending circuits, where the first ascend/descending circuit receives the first signal and the second ascend/descending circuit receives an inverted first signal. Each ascend/descending circuit is operable to descend a high logic level of the received signal to a low output voltage level and ascend a low logic level of the received signal to a high output voltage level. The output voltages from the first and second ascending/descending circuits are input to a sense amplifier that amplifies the difference between the output voltages in order to generate the internal voltage logic levels of the second signal. The first and second ascending/descending circuits buffer their respective received signals using the high logic level of the input signal as a supply voltage. The same principles are also applicable to the level shifting from internal voltage logic levels to external voltage logic levels.

摘要翻译： 公开了一种电平转换器，其可以接收和转换可以具有各种电压逻辑电平的第一信号到具有内部电压逻辑电平的第二信号。 电平移位器包括第一和第二上升/下降电路，其中第一上升/下降电路接收第一信号，第二上升/下降电路接收反相的第一信号。 每个上升/下降电路可操作以将接收信号的高逻辑电平降低到低输出电压电平，并将接收信号的低逻辑电平上升到高输出电压电平。 来自第一和第二上升/下降电路的输出电压被输入到放大输出电压之间的差的读出放大器，以产生第二信号的内部电压逻辑电平。 第一和第二上升/下降电路使用输入信号的高逻辑电平作为电源电压来缓冲它们各自的接收信号。 相同的原理也适用于从内部电压逻辑电平转换到外部电压逻辑电平的电平。

公开(公告)号：US09268636B2

公开(公告)日：2016-02-23

申请号：US13910591

申请日：2013-06-05

申请人： Hoi-ju Chung ,  Su-A Kim ,  Mu-Jin Seo ,  Hak-Soo Yu ,  Jae-Youn Youn ,  Hyo-Jin Choi

发明人： Hoi-ju Chung ,  Su-A Kim ,  Mu-Jin Seo ,  Hak-Soo Yu ,  Jae-Youn Youn ,  Hyo-Jin Choi

IPC分类号： G11C29/00 ,  G06F11/10

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C11/409 ,  G11C29/52 ,  G11C29/783

摘要： A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

摘要翻译： 存储器控制器包括：控制器输入/输出电路，被配置为输出第一命令以读取第一数据，并输出第二命令以读取第一数据的纠错部分。 存储装置包括：误差检测器，数据存储电路和纠错电路。 错误检测器被配置为响应于第一命令来检测从存储器单元读取的数据中的错误位数。 如果检测到的错误比特数大于或等于第一阈值，则数据存储电路被配置为存储读取数据。 误差校正电路被配置为校正存储的数据。

公开(公告)号：US20150049570A1

公开(公告)日：2015-02-19

申请号：US14450537

申请日：2014-08-04

申请人： Sung-Hyun LEE ,  Jun-Hee YOO ,  Dong-Soo KANG ,  Sua KIM ,  Hak-Soo YU ,  Jae-Youn YOUN ,  Hyo-Jin CHOI

发明人： Sung-Hyun LEE ,  Jun-Hee YOO ,  Dong-Soo KANG ,  Sua KIM ,  Hak-Soo YU ,  Jae-Youn YOUN ,  Hyo-Jin CHOI

IPC分类号： G11C8/08 ,  G11C8/10

CPC分类号： G11C8/08 ,  G11C7/1042 ,  G11C7/12 ,  G11C8/10

摘要： In one embodiment, the memory device includes at least one memory bank including first and second subbanks, and control logic configured to control storing data into the memory bank. The control logic is configured to activate the first subbank and to precharge the second subbank in response to a first activate command for the first subbank.

摘要翻译： 在一个实施例中，存储器件包括至少一个包括第一和第二子库的存储体，以及被配置为控制将数据存储到存储体中的控制逻辑。 控制逻辑被配置为响应于第一子银行的第一激活命令来激活第一子库并且预充电第二子库。

公开(公告)号：US08732434B2

公开(公告)日：2014-05-20

申请号：US13437418

申请日：2012-04-02

申请人： Joo Young Hwang ,  Hak Soo Yu

发明人： Joo Young Hwang ,  Hak Soo Yu

IPC分类号： G06F12/02 ,  G06F17/30

CPC分类号： G06F17/30156 ,  G06F12/0238 ,  G06F12/1018 ,  G06F2212/7201

摘要： A memory device includes a hash table storing a hash value, a bit value, and a page address for each of a plurality of pages, a memory cell unit configured to store the pages and output contents corresponding to the page addresses of the pages having a same hash value, and a controller including a comparator configured to compare the contents output from the memory cell unit and change at least one bit value associated with a respective one of the pages upon determining that the contents of the pages are the same.

摘要翻译： 存储装置包括存储多页的散列值，位值和页面地址的哈希表，存储单元单元，被配置为存储页面，并且输出与具有页面的页面的页面地址对应的内容 以及包括比较器的控制器，所述比较器被配置为在确定所述页面的内容相同时比较从所述存储器单元单元输出的内容并改变与所述页面中的相应页面相关联的至少一个位值。

公开(公告)号：US08638621B2

公开(公告)日：2014-01-28

申请号：US13413938

申请日：2012-03-07

申请人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

发明人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

IPC分类号： G11C7/00 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

摘要翻译： 一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。 感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

公开(公告)号：US08553484B2

公开(公告)日：2013-10-08

申请号：US13238553

申请日：2011-09-21

申请人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

发明人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4099

摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.

摘要翻译： 半导体存储器件包括存储单元和第一参考存储单元。 存储单元包括第一开关元件和用于存储数据的第一电容器。 第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。 第一电容器具有用于接收第一板电压的第二端子。 第一参考存储单元包括第一参考开关元件和第一电容器。 第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。 第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。