High-voltage semiconductor component
    37.
    发明授权
    High-voltage semiconductor component 有权
    高压半导体元件

    公开(公告)号:US06960798B2

    公开(公告)日:2005-11-01

    申请号:US10455842

    申请日:2003-06-06

    摘要: A semiconductor component has a semiconductor body comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface is positioned at a distance from the drain zone such that the areas of the first and second conductivity type nested in each other do not reach the drain zone.

    摘要翻译: 半导体部件具有包含阻挡pn结的半导体本体,与第一电极连接的第一导电类型的源区,与形成与第一导电类型互补的第二导电类型的阻挡pn结的区域接壤, 第一导电类型的漏极区连接到第二电极。 面向排水区的第二导电类型的区域的一侧形成第一表面,并且在位于第一表面和漏区之间的第一表面和第二表面之间的区域中,包括第一和第二导电类型的区域 彼此嵌套在一起 第二表面定位在离开排水区一定距离处,使得彼此嵌套的第一和第二导电类型的区域不会到达排水区。

    High voltage resistant edge structure for semiconductor components
    38.
    发明授权
    High voltage resistant edge structure for semiconductor components 有权
    半导体元件耐高压边缘结构

    公开(公告)号:US06870201B1

    公开(公告)日:2005-03-22

    申请号:US09530553

    申请日:1998-11-02

    摘要: The invention relates to a high voltage resistant edge structure in the edge region of a semiconductor component which has floating guard rings of the first conductivity type and inter-ring zones of the second conductivity type which are arranged between the floating guard rings, wherein the conductivities and/or the inter-ring zones are set such that their charge carriers are totally depleted when blocking voltage is applied. The inventive edge structure achieves a modulation of the electrical field both at the surface and in the volume of the semiconductor body. If the inventive edge structure is suitably dimensioned, the field intensity maximum can easily be situated in the depth; that is, in the region of the vertical p-n junction. Thus, a suitable edge construction which permits a “soft” leakage of the electrical field in the volume can always be provided over a wide range of concentrations of p and n doping.

    摘要翻译: 本发明涉及一种半导体元件的边缘区域中的耐高压边缘结构,其具有布置在浮动保护环之间的第一导电类型的浮动保护环和第二导电类型的环形区,其中电导率 和/或环形区域被设置为使得当施加阻断电压时它们的电荷载流子完全耗尽。 本发明的边缘结构在半导体本体的表面和体积上实现了电场的调制。 如果本发明的边缘结构适当地确定尺寸,则场强度最大值可以容易地位于深度中; 也就是在垂直p-n结的区域。 因此,允许在体积中的电场的“软”泄漏的合适的边缘构造总是可以在宽泛的p和n掺杂浓度范围内提供。

    Integrated resistor
    40.
    发明授权
    Integrated resistor 失效
    集成电阻

    公开(公告)号:US6072220A

    公开(公告)日:2000-06-06

    申请号:US206577

    申请日:1998-12-07

    申请人: Helmut Strack

    发明人: Helmut Strack

    摘要: A semiconductor body includes a lightly doped semiconductor zone of a second conductivity type. A first oxide layer is produced on the semiconductor body. A structured polysilicon layer is produced on the oxide layer. The polysilicon layer acts as a mask so that the dopants of one conductivity type are implanted and driven into the surface of the semiconductor zone. A second oxide layer is then produced on the surface of the polysilicon layer and the semiconductor zone. A spacer is etched from this oxide layer. Dopants of the second conductivity type are implanted and driven into the surface of the semiconductor zone. A narrow resistor zone remains lying under the polysilicon layer.

    摘要翻译: 半导体本体包括第二导电类型的轻掺杂半导体区。 在半导体本体上产生第一氧化物层。 在氧化物层上产生结构化的多晶硅层。 多晶硅层用作掩模,使得一种导电类型的掺杂剂被注入并驱动到半导体区的表面中。 然后在多晶硅层和半导体区域的表面上产生第二氧化物层。 从该氧化物层蚀刻间隔物。 将第二导电类型的掺杂剂注入并驱动到半导体区域的表面中。 窄电阻区域仍然位于多晶硅层下面。