公开(公告)号：US20060102907A1

公开(公告)日：2006-05-18

申请号：US11228852

申请日：2005-09-16

Applicant: Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

Inventor： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC: H01L29/04

CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

Abstract translation: 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

公开(公告)号：US09299474B2

公开(公告)日：2016-03-29

申请号：US13812277

申请日：2011-07-28

Applicant: Shinya Morita ,  Aya Miki ,  Yumi Iwanari ,  Toshihiro Kugimiya ,  Satoshi Yasuno ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn

Inventor： Shinya Morita ,  Aya Miki ,  Yumi Iwanari ,  Toshihiro Kugimiya ,  Satoshi Yasuno ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn

IPC: H01B1/08 ,  H01L29/24 ,  C23C14/08 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01B1/08 ,  C23C14/08 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/7869

Abstract: There is provided an oxide for semiconductor layers of thin-film transistors, which oxide can provide thin-film transistors with excellent switching characteristics and by which oxide favorable characteristics can stably be obtained even after the formation of passivation layers. The oxide to be used for semiconductor layers of thin-film transistors according to the present invention includes Zn, Sn, and Si.

Abstract translation: 提供了用于薄膜晶体管的半导体层的氧化物，该氧化物可以提供具有优异的开关特性的薄膜晶体管，并且即使在形成钝化层之后也可以稳定地获得氧化物有利特性。 根据本发明的用于薄膜晶体管的半导体层的氧化物包括Zn，Sn和Si。

公开(公告)号：US09178073B2

公开(公告)日：2015-11-03

申请号：US13989944

申请日：2011-11-28

Applicant: Aya Miki ,  Shinya Morita ,  Toshihiro Kugimiya ,  Satoshi Yasuno ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

Inventor： Aya Miki ,  Shinya Morita ,  Toshihiro Kugimiya ,  Satoshi Yasuno ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

IPC: H01L29/786 ,  C01G19/00 ,  C23C14/08 ,  C23C14/34 ,  H01L21/02 ,  C04B35/453 ,  C23C14/54 ,  C23C14/58 ,  C04B35/01 ,  C04B35/457 ,  H01L27/12

CPC classification number: H01L29/7869 ,  C01G19/006 ,  C01P2006/10 ,  C04B35/01 ,  C04B35/453 ,  C04B35/457 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/3293 ,  C23C14/086 ,  C23C14/3407 ,  C23C14/548 ,  C23C14/5806 ,  C23C14/5873 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/78693

Abstract: This oxide for a semiconductor layer of a thin-film transistor contains Zn, Sn and In, and the content (at %) of the metal elements contained in the oxide satisfies formulas (1) to (3) when denoted as [Zn], [Sn] and [In], respectively. [In]/([In]+[Zn]+[Sn])≧−0.53×[Zn]/([Zn]+[Sn])+0.36 (1) [In]/([In]+[Zn]+[Sn])≧2.28×[Zn]/([Zn]+[Sn])−2.01 (2) [In]/([In]+[Zn]+[Sn])≦1.1×[Zn]/([Zn]+[Sn])−0.32 (3) The present invention enables a thin-film transistor oxide that achieves high mobility and has excellent stress resistance (negligible threshold voltage shift before and after applying stress) to be provided.

Abstract translation: 用于薄膜晶体管的半导体层的氧化物含有Zn，Sn和In，并且当表示为[Zn]时，包含在氧化物中的金属元素的含量（at％）满足式（1）至（3） [Sn]和[In]。 [In] /（[In] + [Zn] + [Sn]）≥-0.53×[Zn] /（[Zn] + [Sn]）+0.36（1）[In] /（[In] ] + [Sn]）≥2.28×[Zn] /（[Zn] + [Sn]）-2.01（2）[In] /（[In] + [Zn] + [Sn]）＆ ] /（[Zn] + [Sn]） - 0.32（3）本发明能够提供实现高迁移率并具有优异的应力阻力（施加应力之前和之后的阈值电压偏移可忽略）的薄膜晶体管氧化物。

公开(公告)号：US08890139B2

公开(公告)日：2014-11-18

申请号：US13534752

申请日：2012-06-27

Applicant: Byung Du Ahn ,  Seung Ho Yeon ,  Sei-Yong Park ,  Mi-Hyae Park ,  Bu Sop Song ,  Tae Gweon Lee ,  Jun Hyun Park ,  Je Hun Lee ,  Jae Woo Park

Inventor： Byung Du Ahn ,  Seung Ho Yeon ,  Sei-Yong Park ,  Mi-Hyae Park ,  Bu Sop Song ,  Tae Gweon Lee ,  Jun Hyun Park ,  Je Hun Lee ,  Jae Woo Park

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/51 ,  G02F1/1362 ,  H01L23/29 ,  C08L83/04 ,  C08G77/16 ,  H01L27/12 ,  C08G77/00 ,  C08G77/20 ,  H01L27/32

CPC classification number: G03F7/0757 ,  C08G77/16 ,  C08G77/20 ,  C08G77/80 ,  C08L83/04 ,  G02F1/136227 ,  G03F7/16 ,  G03F7/20 ,  H01L23/296 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3258 ,  H01L29/517 ,  H01L2924/0002 ,  C08L83/00 ,  H01L2924/00

Abstract: A passivation layer solution composition is provided. A passivation layer solution composition according to an exemplary embodiment of the present invention includes an organic siloxane resin represented by Chemical Formula 1 below. In Chemical Formula 1, R is at least one substituent selected from a saturated hydrocarbon or an unsaturated hydrocarbon having from 1 to about 25 carbon atoms, and x and y may each independently be from 1 to about 200, and wherein each wavy line indicates a bond to an H atom or to an x siloxane unit or a y siloxane unit, or a bond to an x siloxane unit or a y siloxane unit of another siloxane chain comprising x siloxane units or y siloxane units or a combination thereof.

Abstract translation: 提供钝化层溶液组合物。 根据本发明的示例性实施方案的钝化层溶液组合物包括由下述化学式1表示的有机硅氧烷树脂。 在化学式1中，R是选自饱和烃或具有1至约25个碳原子的不饱和烃中的至少一个取代基，x和y各自独立地为1至约200，并且其中每个波浪线表示 键合到H原子或x硅氧烷单元或硅氧烷单元，或与包含x硅氧烷单元或y硅氧烷单元或其组合的另一硅氧烷链的x硅氧烷单元或硅氧烷单元的键。

公开(公告)号：US20130341617A1

公开(公告)日：2013-12-26

申请号：US14004020

申请日：2012-03-08

Applicant: Hiroaki Tao ,  Aya Miki ,  Shinya Morita ,  Satoshi Yasuno ,  Toshihiro Kugimiya ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

Inventor： Hiroaki Tao ,  Aya Miki ,  Shinya Morita ,  Satoshi Yasuno ,  Toshihiro Kugimiya ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

IPC: H01L29/12

CPC classification number: H01L21/02554 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/02587 ,  H01L21/02631 ,  H01L21/477 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7869

Abstract: The oxide of the present invention for thin-film transistors is an In—Zn—Sn-based oxide containing In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide fulfills the following expressions (2) and (4) when [In]/([In]+[Sn])≦0.5; or the following expressions (1), (3), and (4) when [In]/([In]+[Sn])≧0.5. [In]/([In]+[Zn]+[Sn])≦0.3 - - - (1), [In]/([In]+[Zn]+[Sn])≦1.4×{[Zn]/([Zn]+[Sn])}−0.5 - - - (2), [Zn]/([In]+[Zn]+[Sn])≦0.83 - - - (3), and 0.1≦[In]/([In]+[Zn]+[Sn]) - - - (4). According to the present invention, oxide thin films for thin-film transistors can be obtained, which provide TFTs with excellent switching characteristics, and which have high sputtering rate in the sputtering and properly controlled etching rate in the wet etching.

Abstract translation: 用于薄膜晶体管的本发明的氧化物是含有In，Zn和Sn的In-Zn-Sn系氧化物，其中，当In-Zn-Sn系中含有的金属元素的含量（原子％ 当[In] /（[In] + [Sn]）[Zn]，[In] + [Sn]表示[Zn]，[Sn]和[In]时，In-Zn-Sn系氧化物满足下述（2） ]）@ 0.5; 或[In] /（[In] + [Sn]）> = 0.5时的以下表达式（1），（3）和（4）。 [In] + [Zn] + [Sn]）@ 0.3 - - - （1），[In] /（[In] + [Zn] + [Sn]）@ 1.4×{[Zn] /([Zn]+[Sn])}-0.5 - - - （2），[Zn] /（[In] + [Zn] + [Sn]）@ 0.83 - - - （3） In] /（[In] + [Zn] + [Sn]） - - - （4）。 根据本发明，可以获得用于薄膜晶体管的氧化物薄膜，其提供具有优异的开关特性的TFT，并且在溅射中具有高溅射速率并且在湿蚀刻中具有适当控制的蚀刻速率。

公开(公告)号：US08558230B2

公开(公告)日：2013-10-15

申请号：US12756323

申请日：2010-04-08

Applicant: Dong-Hoon Lee ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hee-Tae Kim ,  Chang-Oh Jeong ,  Pil-Sang Yun ,  Ki-Won Kim

Inventor： Dong-Hoon Lee ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hee-Tae Kim ,  Chang-Oh Jeong ,  Pil-Sang Yun ,  Ki-Won Kim

IPC: H01L29/04 ,  H01L29/10

CPC classification number: H01L27/1225 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/7869

Abstract: A thin film transistor (TFT) substrate and a method of fabricating the same are provided. The thin film transistor substrate may have low resistance characteristics and may have reduced mutual diffusion and contact resistance between an active layer pattern and data wiring. The thin film transistor substrate may include gate wiring formed on an insulating substrate. Oxide active layer patterns may be formed on the gate wiring and may include a first substance. Data wiring may be formed on the oxide active layer patterns to cross the gate wiring and may include a second substance. Barrier layer patterns may be disposed between the oxide active layer patterns and the data wiring and may include a third substance.

Abstract translation: 提供薄膜晶体管（TFT）基板及其制造方法。 薄膜晶体管基板可以具有低电阻特性，并且可以减少有源层图案和数据布线之间的相互扩散和接触电阻。 薄膜晶体管基板可以包括形成在绝缘基板上的栅极布线。 氧化物有源层图案可以形成在栅极布线上，并且可以包括第一物质。 数据布线可以形成在氧化物有源层图案上以跨越栅极布线，并且可以包括第二物质。 阻挡层图案可以设置在氧化物活性层图案和数据布线之间，并且可以包括第三物质。

公开(公告)号：US08507956B2

公开(公告)日：2013-08-13

申请号：US13051904

申请日：2011-03-18

Applicant: Je-Hun Lee ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

Inventor： Je-Hun Lee ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

IPC: H01L33/00 ,  H01L29/43 ,  H01L29/49 ,  H01L29/76

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L29/4908

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including a copper layer and a copper solid solution layer.

Abstract translation: 提供线结构，制造线的方法，薄膜晶体管（TFT）基板和制造TFT基板的方法。 导线结构包括在基板上形成的包含铜层和铜固溶体层的阻挡层。

公开(公告)号：US08492770B2

公开(公告)日：2013-07-23

申请号：US13035054

申请日：2011-02-25

Applicant: Jae-Woo Park ,  Je-Hun Lee ,  Seong-Jin Lee ,  Yeon-Hong Kim

Inventor： Jae-Woo Park ,  Je-Hun Lee ,  Seong-Jin Lee ,  Yeon-Hong Kim

IPC: H01L29/786

CPC classification number: H01L29/04 ,  H01L29/786

Abstract: A thin film transistor includes a gate electrode formed on a substrate, a semiconductor pattern overlapped with the gate electrode, a source electrode overlapped with a first end of the semiconductor pattern and a drain electrode overlapped with a second end of the semiconductor pattern and spaced apart from the source electrode. The semiconductor pattern includes an amorphous multi-elements compound including a II B element and a VI A element or including a III A element and a V A element and having an electron mobility no less than 1.0 cm2/Vs and an amorphous phase, wherein the VI A element excludes oxygen. Thus, a driving characteristic of the thin film transistor may be improved.

Abstract translation: 薄膜晶体管包括形成在基板上的栅极电极，与栅电极重叠的半导体图案，与半导体图案的第一端重叠的源电极和与半导体图案的第二端重叠并分开的漏电极 源极电极。 半导体图案包括包含IIB元素和VIA元素或包含IIIA元素和VA元素并且具有不小于1.0cm 2 / Vs的电子迁移率的无定形多元素化合物和非晶相，其中VI 一个元素排除氧气。 因此，可以提高薄膜晶体管的驱动特性。

公开(公告)号：US20130181212A1

公开(公告)日：2013-07-18

申请号：US13543235

申请日：2012-07-06

Applicant: Gun Hee KIM ,  Jae Woo PARK ,  Jin Hyun PARK ,  Byung Du AHN ,  Je Hun LEE ,  Yeon Hong KIM ,  Jung Hwa KIM ,  Sei-Yong PARK ,  Jun Hyun PARK ,  Kyoung Won LEE ,  Ji Hun LIM

Inventor： Gun Hee KIM ,  Jae Woo PARK ,  Jin Hyun PARK ,  Byung Du AHN ,  Je Hun LEE ,  Yeon Hong KIM ,  Jung Hwa KIM ,  Sei-Yong PARK ,  Jun Hyun PARK ,  Kyoung Won LEE ,  Ji Hun LIM

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L21/02554

Abstract: A semiconductor device includes: a substrate, a semiconductor layer including an oxide semiconductor disposed on the substrate, a barrier layer disposed on the semiconductor layer and an insulating layer disposed on the barrier layer. The semiconductor layer includes an oxide semiconductor, and the barrier layer includes a material having a lower standard electrode potential than a semiconductor material of the oxide semiconductor, a lower electron affinity than the semiconductor material of the oxide semiconductor, or a larger band gap than the semiconductor material of the oxide semiconductor. The insulating layer includes at least one of a silicon-based oxide or a silicon-based nitride, and the insulating layer includes a portion which contacts with an upper surface of the barrier layer.

Abstract translation: 半导体器件包括：衬底，包括设置在衬底上的氧化物半导体的半导体层，设置在半导体层上的阻挡层和设置在阻挡层上的绝缘层。 半导体层包括氧化物半导体，并且阻挡层包括具有比氧化物半导体的半导体材料低的标准电极电位的材料，比氧化物半导体的半导体材料低的电子亲和力或比 氧化物半导体的半导体材料。 绝缘层包括硅基氧化物或硅基氮化物中的至少一种，并且绝缘层包括与阻挡层的上表面接触的部分。

公开(公告)号：US08416897B2

公开(公告)日：2013-04-09

申请号：US12561076

申请日：2009-09-16

Applicant: Il-Gu Lee ,  Hyun-Gu Park ,  Je-Hun Lee ,  Sok-Kyu Lee

Inventor： Il-Gu Lee ,  Hyun-Gu Park ,  Je-Hun Lee ,  Sok-Kyu Lee

IPC: H04B7/10 ,  H04L27/06

CPC classification number: H04W52/028 ,  H04L2027/0016 ,  H04L2027/0067 ,  H04W52/0245 ,  Y02D70/142

Abstract: An apparatus for reducing power consumption of a receiver in a high-speed wireless communication system and a control method thereof are provided. The apparatus for processing a signal in a receiver of a wireless communication system includes a carrier sensor configured to sense a carrier used in the wireless communication system, a decoder configured to decode the detected carrier signal to a signal and data, and a controller configured to control supplying power and a clock only to the carrier sensor during carrier sensing, and supplying power and a clock to an overall receiver when a carrier is sensed.

Abstract translation: 提供一种用于降低高速无线通信系统中的接收机的功耗的装置及其控制方法。 用于处理无线通信系统的接收机中的信号的装置包括被配置为感测在无线通信系统中使用的载波的载波传感器，被配置为将检测到的载波信号解码为信号和数据的解码器，以及控制器， 在载波检测期间仅控制向载波传感器提供功率和时钟，并且当检测到载波时，向整个接收机提供功率和时钟。