公开(公告)号：US07259978B2

公开(公告)日：2007-08-21

申请号：US11221684

申请日：2005-09-08

申请人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

摘要翻译： 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

公开(公告)号：US07242602B2

公开(公告)日：2007-07-10

申请号：US11002034

申请日：2004-12-02

申请人： Chang-Ho Lee ,  Jong-Hyun Choi

发明人： Chang-Ho Lee ,  Jong-Hyun Choi

IPC分类号： G11C5/08 ,  G11C5/06 ,  G11C11/12

CPC分类号： G11C11/4097 ,  G11C5/14 ,  G11C7/02 ,  Y10S257/907

摘要： A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend parallel to the memory device word lines, and can provide a power supply ground and/or signal line.

摘要翻译： 半导体存储器件包括间隔开的扭曲位线对，其相应的一个包括间隔开的扭曲区域。 导线与间隔开的扭绞线对的相应扭曲区域重叠。 导线可以平行于存储器件字线延伸，并且可以提供电源接地和/或信号线。

公开(公告)号：US20070153590A1

公开(公告)日：2007-07-05

申请号：US11567826

申请日：2006-12-07

申请人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

发明人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes, a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuits and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated white the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

摘要翻译： 一种内部参考电压发生电路，其将待机电流和半导体存储器件的引脚数量减少，其中参考电压被提供给通过连接有管芯发送器电阻器的输入接收信号的输入缓冲器， 包括：通过电源电压输出所述参考电压的分压电路; 连接到分压电路的一端的下拉驱动器; 以及校准控制电路，其比较输入的电压电平和分压电路的端部的电压电平，并根据比较的结果控制下拉驱动器的导通电阻值。 内部参考电压产生电路白色运行，存储器控制器将信号输入到模式寄存器组（MRS）中以使能内部参考电压产生电路，并且MRS的输出信号被激活。

公开(公告)号：US20070070782A1

公开(公告)日：2007-03-29

申请号：US11515799

申请日：2006-09-06

申请人： Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

发明人： Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

IPC分类号： G11C8/00

CPC分类号： G11C8/06 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/225

摘要： Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the input buffer is enabled only when the second signal shows a non-power down mode and the first signal shows a chip selection state. The input buffer is at least one selected from the group consisting of a row address strobe input buffer, a column address strobe input buffer, and an address input buffer.

摘要翻译： 提供了存储器件，存储器控制器和使用它的存储器系统的输入缓冲器。 响应于表示芯片选择信息的第一信号和表示掉电信息的第二信号，存储器件的输入缓冲器被使能或禁止，并且仅当第二信号显示非掉电模式时，输入缓冲器被使能，并且 第一信号显示芯片选择状态。 输入缓冲器是从由行地址选通输入缓冲器，列地址选通输入缓冲器和地址输入缓冲器组成的组中选择的至少一个。

公开(公告)号：US20060176079A1

公开(公告)日：2006-08-10

申请号：US11348582

申请日：2006-02-06

申请人： Jong-Hyun Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Young-Hun Seo

IPC分类号： H03K19/0175

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/0005

摘要： An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.

摘要翻译： 一种用于半导体存储器件的输入/输出电路，包括数据输出电路，配置为响应于输入/输出使能信号缓冲半导体存储器件中的输出数据，以将缓冲的输出数据输出到输入/输出信号线， 数据输入电路，被配置为从输入/输出信号线接收输入数据并缓冲输入数据以将缓冲的输入数据传送到半导体存储器件;以及负载控制器，被配置为响应于控制输入/输出信号线上的负载 到输入/输出使能信号。

公开(公告)号：US20060062060A1

公开(公告)日：2006-03-23

申请号：US11229918

申请日：2005-09-19

申请人： Young-sun Min ,  Nam-jong Kim ,  Jong-hyun Choi

发明人： Young-sun Min ,  Nam-jong Kim ,  Jong-hyun Choi

IPC分类号： G11C29/00

CPC分类号： G11C29/82 ,  G11C17/18

摘要： A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.

摘要翻译： 可以通过生成与存储器件中的故障存储器位置的多个地址相对应的多个故障地址信号，然后将失败存储器位置的多个地址编程到故障存储器位置的多个地址来对 编程单元供读取或写入操作期间冗余电路用于故障存储单元的多个地址。

公开(公告)号：US06992943B2

公开(公告)日：2006-01-31

申请号：US10959804

申请日：2004-10-06

申请人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

发明人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

IPC分类号： G11C7/00

CPC分类号： G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

摘要： Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or 1/16) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

公开(公告)号：US20050122820A1

公开(公告)日：2005-06-09

申请号：US11005523

申请日：2004-12-06

申请人： Jong-Hyun Choi ,  Mi-Jo Kim ,  Kwang-Sook Noh ,  Beob-Rae Cho

发明人： Jong-Hyun Choi ,  Mi-Jo Kim ,  Kwang-Sook Noh ,  Beob-Rae Cho

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C7/20 ,  G11C11/4074

CPC分类号： G11C11/4074 ,  G11C5/143 ,  G11C7/20 ,  G11C2207/2227

摘要： A semiconductor device includes a memory and a power voltage interrupter configured to interrupt an external power voltage applied to circuitry of the semiconductor device responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of the memory. A power voltage shifter is configured to shift a power voltage in the circuitry to a specific level responsive to the DPD command signal.

摘要翻译： 半导体器件包括存储器和电源电压中断器，其被配置为响应于在存储器的DPD模式中产生的深度掉电（DPD）命令信号来中断施加到半导体器件的电路的外部电源电压。 电源电压移位器被配置为响应于DPD命令信号将电路中的电源电压移动到特定电平。

公开(公告)号：US20050078548A1

公开(公告)日：2005-04-14

申请号：US10951881

申请日：2004-09-29

申请人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

发明人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/10 ,  G11C29/46

CPC分类号： G11C7/1045 ,  G11C29/46

摘要： A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

摘要翻译： 用于设置存储器件的操作模式的存储器系统，存储器件和方法包括存储器单元阵列; 行和列解码器，其分别根据多位地址信号选择存储单元阵列的行和列; 以及模式控制电路，其从在行或列的选择中使用的多位地址信号接收至少一个位，并且根据至少一个位设置存储器件的操作模式，其中操作 模式是突发长度模式，DLL复位模式，测试模式，CAS延迟模式和突发类型模式之一。

公开(公告)号：US06661722B2

公开(公告)日：2003-12-09

申请号：US10190652

申请日：2002-07-08

申请人： Jae-young Lee ,  Jong-hyun Choi

发明人： Jae-young Lee ,  Jong-hyun Choi

IPC分类号： G11C700

CPC分类号： H01L27/0207 ,  G11C7/065

摘要： A bit line sense amplifier is provided. The bit line sense amplifier includes a first sense amplifier block in which a plurality of first sense amplifiers for sensing and amplifying data of a bit line or a complementary bit line are laid out, and first drivers, which are arranged outside the plurality of first sense amplifiers, for pulling down the bit line or the complementary bit line to a first voltage level. The bit line sense amplifier further includes a second sense amplifier block with a plurality of second sense amplifiers and second drivers for pulling up the bit line or the complementary bit line to a second voltage level. By arranging the drivers outside the bit sense amplifiers, effects caused by variation in critical dimensions (CDs) of gates are minimized and the entire area of the bit line sense amplifier is reduced.

摘要翻译： 提供位线读出放大器。 位线读出放大器包括第一读出放大器块，其中布置用于感测和放大位线或互补位线的数据的多个第一读出放大器，并且布置在多个第一感测之外的第一驱动器 放大器，用于将位线或互补位线拉低至第一电压电平。 位线读出放大器还包括具有多个第二读出放大器的第二读出放大器模块和用于将位线或互补位线提升到第二电压电平的第二驱动器。 通过将驱动器布置在位读出放大器之外，由栅极的关键尺寸（CD）的变化引起的影响被最小化，并且位线读出放大器的整个区域减小。