公开(公告)号：US20070200162A1

公开(公告)日：2007-08-30

申请号：US11361330

申请日：2006-02-24

申请人： Kuo-Chi Tu ,  Chun-Yao Chen ,  Yi-Ching Lin

发明人： Kuo-Chi Tu ,  Chun-Yao Chen ,  Yi-Ching Lin

IPC分类号： H01L29/76

CPC分类号： H01L28/40 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/56

摘要： A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.

摘要翻译： 提供了具有改进的感测速度和可靠性的记忆装置及其形成方法。 存储器件包括在半导体衬底上具有低k值的第一电介质层，在第一介电层上具有第二k值的第二电介质层和形成在第二电介质层中的电容器，其中电容器包括位于 最少部分地被第三介电层填充。 存储器件还包括第二电介质层上的第三电介质层和第三电介质层上的位线。 位线电耦合到电容器。 优选地，在电容器的杯区域中形成具有大尺寸的空隙。

公开(公告)号：US20070063251A1

公开(公告)日：2007-03-22

申请号：US11233344

申请日：2005-09-22

申请人： Kuo-Chi Tu ,  Hsiang-Fan Lee

发明人： Kuo-Chi Tu ,  Hsiang-Fan Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  Y10S257/904

摘要： A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device formed therein and a volatile memory device having a volatile memory device formed therein. Gate electrode and capacitor plate layer components within each of the devices may be formed simultaneously incident to patterning of a single blanket gate electrode material layer

摘要翻译： 半导体产品和半导体产品的制造方法采用半导体衬底。 半导体衬底具有其中形成有逻辑器件的逻辑区域，其中形成有非易失性存储器件的非易失性存储器区域和其中形成有易失性存储器件的易失性存储器件。 可以在每个器件内的栅电极和电容器板层组件同时入射到单个覆盖栅极电极材料层的图案化

公开(公告)号：US07163853B2

公开(公告)日：2007-01-16

申请号：US11054448

申请日：2005-02-09

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/338

CPC分类号： H01L27/10873 ,  H01L21/28079 ,  H01L27/10805 ,  H01L27/1085 ,  H01L28/60 ,  H01L29/495 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/926

摘要： A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom electrode layer in the capacitor trench, removing the dummy gate to provide a gate trench, forming a dielectric layer in the capacitor trench and the gate trench, and forming a metal layer over the dielectric layer in the capacitor trench and the gate trench.

摘要翻译： 在半导体器件上制造电容器和金属栅极的方法包括在衬底上形成虚拟栅极，在衬底上形成沟槽层并与伪栅极相邻，在沟槽层中形成电容器沟槽，形成底部电极层 在电容器沟槽中，去除伪栅极以提供栅极沟槽，在电容器沟槽和栅极沟槽中形成介电层，并在电容器沟槽和栅极沟槽中的介电层上形成金属层。

公开(公告)号：US07019348B2

公开(公告)日：2006-03-28

申请号：US10789527

申请日：2004-02-26

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L21/76232 ,  H01L21/76229

摘要： An embedded semiconductor product employs a first isolation trench and first isolation region formed therein adjoining a logic cell active region of a semiconductor substrate. The embedded semiconductor product also employs a second isolation trench and second isolation region formed therein adjoining a memory cell active region of the semiconductor substrate. The second isolation trench is deeper than the first isolation trench such that a storage capacitor whose capacitor plate is embedded at least in part within the second isolation region may be formed with enhanced capacitance.

摘要翻译： 嵌入式半导体产品采用第一隔离沟槽和形成在其中的与半导体衬底的逻辑单元有源区相邻的第一隔离区。 嵌入式半导体产品还采用与半导体衬底的存储单元有源区相邻形成的第二隔离沟道和第二隔离区。 第二隔离沟槽比第一隔离沟槽更深，使得其电容器板至少部分地嵌入在第二隔离区域内的存储电容器可以形成为增强的电容。

公开(公告)号：US20060008976A1

公开(公告)日：2006-01-12

申请号：US11223287

申请日：2005-09-09

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/8234

CPC分类号： H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

摘要： A process for fabricating a novel random access memory (RAM) capacitor in a shallow trench isolation (STI) The method utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel photoresist mask is used to etch bottle-shaped recesses in the STI under a first hard mask. After forming bottom electrodes in the recesses and forming an interelectrode dielectric layer, a conducting layer is deposited sufficiently thick to fill the recesses and to form a planar surface, and a second hard mask is deposited. The conducting layer is patterned to form the capacitor top electrodes. This reduced topography results in reduced leakage currents when the gate electrodes are formed over the capacitor top electrodes.

摘要翻译： 用于制造浅沟槽隔离（STI）中的新型随机存取存储器（RAM）电容器的方法该方法利用新颖的节点光刻胶掩模，用于STI中的等离子体蚀刻凹槽，以防止衬底中的等离子体蚀刻引起的缺陷。 该新型光刻胶掩模用于蚀刻第一硬掩模下STI中的瓶形凹槽。 在凹陷中形成底部电极并形成电极间电介质层之后，将导电层沉积得足够厚以填充凹部并形成平坦表面，并且沉积第二硬掩模。 将导电层图案化以形成电容器顶部电极。 当栅电极形成在电容器顶部电极上时，这种减小的形状导致减小的漏电流。

公开(公告)号：US20050151183A1

公开(公告)日：2005-07-14

申请号：US10757203

申请日：2004-01-14

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

摘要： A process for fabricating a novel random access memory (RAM) capacitor in a shallow trench isolation (STI). The method utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel photoresist mask is used to etch bottle-shaped recesses in the STI under a first hard mask. After forming bottom electrodes in the recesses and forming an interelectrode dielectric layer, a conducting layer is deposited sufficiently thick to fill the recesses and to form a planar surface, and a second hard mask is deposited. The conducting layer is patterned to form the capacitor top electrodes. This reduced topography results in reduced leakage currents when the gate electrodes are formed over the capacitor top electrodes.

摘要翻译： 一种在浅沟槽隔离（STI）中制造新型随机存取存储器（RAM）电容器的工艺。 该方法利用新颖的节点光刻胶掩模，用于STI中的等离子体蚀刻凹槽，以防止基板中的等离子体蚀刻引起的缺陷。 该新型光刻胶掩模用于蚀刻第一硬掩模下STI中的瓶形凹槽。 在凹陷中形成底部电极并形成电极间电介质层之后，将导电层沉积得足够厚以填充凹部并形成平坦表面，并且沉积第二硬掩模。 将导电层图案化以形成电容器顶部电极。 当栅极形成在电容器顶部电极上时，这种减小的形状导致减小的漏电流。

公开(公告)号：US20050124133A1

公开(公告)日：2005-06-09

申请号：US10729084

申请日：2003-12-05

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/105 ,  H01L29/92

CPC分类号： H01L27/11526 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11543 ,  H01L28/40

摘要： A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor in a mixed mode semiconductor device. A floating gate of a split gate transistor and a bottom electrode of a PIP capacitor are formed from a first polysilicon layer using a single lithography mask. Poly-oxide regions are formed over the floating gate and the bottom electrode, and an oxide layer is formed over the poly-oxide regions and other exposed material layers. A nitride layer is deposited over the oxide layer. The nitride layer is patterned to expose at least a portion of the poly-oxide region over the bottom electrode. The exposed oxide layer and poly-oxide region are removed from over the bottom electrode. A second polysilicon layer is deposited over the structure, and a control gate of the split gate transistor and a top electrode of the PIP capacitor are formed from the second polysilicon layer using a single lithography mask.

摘要翻译： 一种在混合模式半导体器件中形成多晶硅 - 绝缘体 - 多晶硅（PIP）电容器的方法。 分离栅极晶体管的浮置栅极和PIP电容器的底部电极由使用单个光刻掩模的第一多晶硅层形成。 多晶氧化物区域形成在浮置栅极和底部电极上，并且氧化物层形成在多晶氧化物区域和其它暴露的材料层上。 在氧化物层上沉积氮化物层。 图案化氮化物层以暴露底部电极上的多晶氧化物区域的至少一部分。 暴露的氧化物层和多晶氧化物区域从底部电极上去除。 在结构上沉积第二多晶硅层，并且使用单个光刻掩模由第二多晶硅层形成分离栅极晶体管的控制栅极和PIP电容器的顶部电极。

公开(公告)号：US06872622B1

公开(公告)日：2005-03-29

申请号：US10119335

申请日：2002-04-09

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/84 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3212 ,  H01L27/10811 ,  H01L27/10888

摘要： A process for fabricating a capacitor under bit line (CUB), DRAM device, featuring increased capacitor storage node surface area, and increased overlay margin between storage node and bit line structures, has been developed. The process features the definition of hemispherical grain (HSG) silicon storage node shapes formed in storage node openings, and the definition of connecting HSG shapes formed in openings located adjacent to the storage node openings. This is accomplished dry etching procedures applied to portions of the HSG silicon layer not protected by a photoresist shape which in turn was obtained via partial exposure of, and development of, a photoresist layer. A polysilicon top plate structure, formed via polysilicon deposition and a following CMP procedure, results in a capacitor structure comprised with increased surface area as a result of the connected HSG silicon shapes. The ability to increase surface area via the connecting HSG silicon shapes allow ample space for definition of a bit line contact structure in a region located between capacitor structures.

摘要翻译： 已经开发了一种用于在位线（CUB）下制造电容器的过程，具有增加的电容器存储节点表面积的DRAM器件以及存储节点和位线结构之间的增加的覆盖裕度。 该过程的特征在于存储节点开口中形成的半球形晶粒（HSG）硅储存节点形状的定义，以及形成在与存储节点开口相邻的开口中形成的连接HSG形状的定义。 这是对不被光致抗蚀剂形状保护的HSG硅层的部分施加的干蚀刻程序，其又通过部分曝光和显影光致抗蚀剂层获得。 通过多晶硅沉积和随后的CMP程序形成的多晶硅顶板结构导致由于连接的HSG硅形状而具有增加的表面积的电容器结构。 通过连接的HSG硅形状增加表面积的能力允许在位于电容器结构之间的区域中定义位线接触结构的充足空间。

公开(公告)号：US06642097B2

公开(公告)日：2003-11-04

申请号：US10292025

申请日：2002-11-12

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/91

摘要： A novel method and structure are described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After insulating the FETs with a first insulating layer, a second insulating layer is deposited and first openings are etched for capacitor bottom electrodes. A first conducting layer is deposited. The second openings are recessed to the first conducting layer. The first conducting layer is removed and the underlying second insulating layer is recessed. A thin interelectrode layer is deposited. A second conducting layer is deposited to fill the first and second openings, and is polished back to form a novel structure having capacitor top plates that are auto-self-aligned to the second insulating layer over the bit-line contacts. This allows for increased overlay margins and increases cell density.

摘要翻译： 描述了一种新颖的方法和结构，用于制造具有改善位线和电容器顶部电极之间覆盖边缘的电容器下位线（CUB）DRAM单元。 在用第一绝缘层绝缘FET之后，沉积第二绝缘层，并且蚀刻用于电容器底部电极的第一开口。 沉积第一导电层。 第二开口凹入到第一导电层。 第一导电层被去除并且下面的第二绝缘层凹进。 沉积薄的电极间层。 沉积第二导电层以填充第一和第二开口，并被抛光以形成具有电容器顶板的新颖结构，其在位线触点上与第二绝缘层自动对准。 这允许增加覆盖边缘并增加细胞密度。

公开(公告)号：US09048212B2

公开(公告)日：2015-06-02

申请号：US13472304

申请日：2012-05-15

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/02 ,  H01L49/02

CPC分类号： H01L28/75 ,  H01L21/32134 ,  H01L28/40 ,  H01L28/60 ,  H01L28/65 ,  H01L28/92

摘要： Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a capacitor over a workpiece. The capacitor includes a bottom electrode, a capacitor dielectric disposed over the bottom electrode, and a top electrode disposed over the capacitor dielectric. A portion of the bottom electrode and a portion of the top electrode are removed proximate edges of the capacitor dielectric.

摘要翻译： 公开了半导体器件，其制造方法以及制造电容器的方法。 在一个实施例中，制造半导体器件的方法包括在工件上形成电容器。 电容器包括底电极，设置在底电极上的电容器电介质和设置在电容器电介质上的顶电极。 底部电极的一部分和顶部电极的一部分在电容器电介质的边缘附近被去除。