公开(公告)号：US20100293324A1

公开(公告)日：2010-11-18

申请号：US12844354

申请日：2010-07-27

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G11C29/765 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/023 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址。

公开(公告)号：US20090046501A1

公开(公告)日：2009-02-19

申请号：US12182996

申请日：2008-07-30

Applicant: Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Mahmud ASSAR

Inventor： Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Mahmud ASSAR

IPC: G11C11/14 ,  H01L21/00 ,  G11C11/34

CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die.

Abstract translation: 闪存RAM存储器包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器， 易失性RAM驻留在单片模具上。

公开(公告)号：US07174445B2

公开(公告)日：2007-02-06

申请号：US10115117

申请日：2002-04-01

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: A43C9/06

CPC classification number: G11C7/20 ,  G06F13/387 ,  G06F13/4081 ,  G06F2213/0042 ,  G11C7/1045

Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols. Upon initialization with the interface device, the flash memory card automatically detects the selected operating mode of the interface device and configures itself to operate with the selected operating mode. The operating mode detection is accomplished by sensing unencoded signals and encoded signals. The encoded signals are encoded with a finite set of predetermined codes. Each predetermined code uniquely identifies a particular operating mode.

Abstract translation: 一种接口系统，在主计算机系统和闪存卡之间以选定的操作模式促进用户友好的连接。 接口系统包括接口设备和闪存卡。 接口系统具有显着扩展闪存卡内的工作模式检测功能，并显着减少了操作模式的错误检测。 接口设备包括用于耦合到主计算机的第一端和用于耦合到闪存卡的第二端，同时支持主机计算机系统也支持的所选操作模式中的通信。 闪存卡利用五十针连接通过接口设备与主机系统进行接口。 闪存卡的五十针连接可以在各种配置中使用，例如通用串行模式，PCMCIA模式和ATA IDE模式。 这些操作模式中的每一种都需要不同的协议。 在使用接口设备进行初始化时，闪存卡会自动检测接口设备的选定操作模式，并配置自身以所选择的操作模式进行操作。 通过感测未编码的信号和编码信号来实现操作模式检测。 编码信号用有限的一组预定码进行编码。 每个预定代码唯一地标识特定的操作模式。

公开(公告)号：US06411546B1

公开(公告)日：2002-06-25

申请号：US09565517

申请日：2000-05-05

Applicant: Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

IPC: G11C1604

CPC classification number: G11C16/102 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G11C8/12 ,  G11C16/08

Abstract: An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.

Abstract translation: 公开了本发明的实施例，其包括用于控制对由行和列组成的非易失性存储器阵列执行的擦除操作的非易失性存储器系统，非易失性存储器阵列存储组织成块的数字信息，每个块具有一个或多个信息扇区 并且每个扇区具有用户数据字段和扩展字段，并且每个扇区存储在存储器阵列的行内。 控制器电路耦合到主机电路并且可操作以对非易失性存储器阵列执行擦除操作，控制器电路擦除所识别的具有特定用户数据字段和特定扩展字段的信息扇区，其中特定用户字段和特定用户字段 扩展字段被分别擦除。

公开(公告)号：US5845313A

公开(公告)日：1998-12-01

申请号：US509706

申请日：1995-07-31

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G11C16/08 ,  G11C16/10 ,  G11C29/00 ,  G06F12/10

CPC classification number: G11C29/765 ,  G06F12/023 ,  G06F12/0246 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82 ,  G06F11/1068

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid erase cycles each time information stored in the mass storage is changed. Erase cycle are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address

Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免擦除循环。 通过将更改后的数据文件编程为空的大容量存储块而不是将其自身作为硬盘来避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址

公开(公告)号：US5523724A

公开(公告)日：1996-06-04

申请号：US293676

申请日：1994-08-19

Applicant: Mahmud Assar ,  Petro Estakhri ,  Boyd Pett

Inventor： Mahmud Assar ,  Petro Estakhri ,  Boyd Pett

IPC: H03L7/089 ,  H03L7/10 ,  H03L3/00 ,  H03L7/08

CPC classification number: H03L7/0895 ,  H03L7/10 ,  H03L2207/08

Abstract: A low power clocking circuit includes a crystal oscillator for generating a digital signal having a first frequency. The first frequency is relatively slow which allows the crystal oscillator to consume reduced power. The phase detector signal is coupled to control a charge pump circuit that generates a voltage on an output node for controlling a voltage controlled oscillator. The VCO generates a clock signal having a second frequency that is higher than the first frequency. The charge pump circuit includes an active mode and a power down mode and is operatively coupled between a first supply voltage and a second supply voltage. As typically provided, the charge pump includes a capacitor network coupled to the output node for maintaining the output voltage. The charge pump includes a voltage control circuit having an up input for increasing the output voltage and a down input for decreasing the output voltage. In addition, a ring enable input is provided for open circuiting all electrical paths from the first supply voltage to the second supply voltage and a precharge circuit is provided for maintaining the output voltage at a predetermined precharge level during the power down mode. Finally, a jump start input controls a jump start circuit for rapidly driving the output voltage to a predetermined level while the charge pump circuit transitions from a power down mode to an active mode. The jump start input includes a single pulse of the digital signal.

Abstract translation: 低功率时钟电路包括用于产生具有第一频率的数字信号的晶体振荡器。 第一个频率相对较慢，这允许晶体振荡器消耗功率。 相位检测器信号被耦合以控制在输出节点上产生电压以控制压控振荡器的电荷泵电路。 VCO产生具有高于第一频率的第二频率的时钟信号。 电荷泵电路包括有源模式和掉电模式，并且可操作地耦合在第一电源电压和第二电源电压之间。 如通常提供的，电荷泵包括耦合到输出节点的电容器网络，用于维持输出电压。 电荷泵包括具有用于增加输出电压的上输入的电压控制电路和用于降低输出电压的下降输入。 此外，提供环形使能输入用于开路从第一电源电压到第二电源电压的所有电气路径，并且提供预充电电路用于在掉电模式期间将输出电压保持在预定的预充电电平。 最后，跳跃启动输入控制用于在电荷泵电路从断电模式转换到活动模式的同时将输出电压快速驱动到预定电平的跳跃启动电路。 跳跃启动输入包括数字信号的单个脉冲。

公开(公告)号：US5485595A

公开(公告)日：1996-01-16

申请号：US131495

申请日：1993-10-04

Applicant: Mahmud Assar ,  Petro Estakhri ,  Siamack Nemazie ,  Mahmood Mozaffari

Inventor： Mahmud Assar ,  Petro Estakhri ,  Siamack Nemazie ,  Mahmood Mozaffari

IPC: G06F3/06 ,  G06F12/02 ,  G11C16/10 ,  G11C16/34 ,  G06F12/14

CPC classification number: G11C16/105 ,  G06F12/0246 ,  G06F12/0292 ,  G06F3/0601 ,  G11C16/102 ,  G11C16/349 ,  G11C16/3495 ,  G06F2003/0694 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit and method are provided for evenly using all blocks in the mass storage. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old versions of a block, a count to determine the number of times a block has been erased and written and an erase inhibit flag. Reading is performed by providing the logical block address to the memory storage. The system sequentially compares the stored logical block addresses until it finds a match. That data file is then coupled to the system.

Abstract translation: 半导体大容量存储装置可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，该设备避免擦除循环。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 其次，提供了用于均匀地使用大容量存储器中的所有块的电路和方法。 这些优点通过使用几个标志来实现，地图将块的逻辑地址与该块的物理地址和每个块的计数寄存器相关联。 特别地，为缺陷块，使用块，块的旧版本提供标志，确定块被擦除和写入的次数的计数和擦除禁止标志。 通过向存储器存储器提供逻辑块地址来执行读取。 系统顺序地比较存储的逻辑块地址，直到找到匹配。 然后将该数据文件耦合到系统。

公开(公告)号：US5300835A

公开(公告)日：1994-04-05

申请号：US16574

申请日：1993-02-10

Applicant: Mahmud Assar ,  Prakash C. Agarwal ,  Vlad Bril

Inventor： Mahmud Assar ,  Prakash C. Agarwal ,  Vlad Bril

IPC: H01L27/118 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/0175

CPC classification number: H03K19/018521 ,  H01L27/11898 ,  H03K19/0027 ,  H03K19/018585 ,  H03K19/018592 ,  H03K2217/0018

Abstract: This invention describes the design and implementation of a low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The invention further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels.

Abstract translation: 本发明描述了低功率CMOS双向I / O缓冲器的设计和实现，其将低电压核心逻辑电平信号转换为最高逻辑电平信号以驱动输出可选逻辑电平信号的最终输出级。 本发明还将各种逻辑电平的输入信号转换为低电压核心逻辑电平信号。 在任一情况下，在需要电压转换来表示适当的二进制逻辑电平的混合电源环境中AC和DC功耗被最小化。

公开(公告)号：US08477530B2

公开(公告)日：2013-07-02

申请号：US13305646

申请日：2011-11-28

Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

IPC: G11C11/14

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.

公开(公告)号：US08391058B2

公开(公告)日：2013-03-05

申请号：US13345600

申请日：2012-01-06

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud Assar

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud Assar

IPC: G11C11/14

CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract translation: 闪存RAM存储器包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器， 易失性RAM驻留在单片模具上。 非易失性RAM由以三维形式布置的磁存储单元堆叠形成，用于更高密度和更低成本。