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72 条记录 (耗时 0.029 秒)

    Memory device
    31.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US06226203B1

    公开(公告)日：2001-05-01

    申请号：US09502470

    申请日：2000-02-11

    申请人： Akira Kikutake ,  Masato Matsumiya ,  Satoshi Eto ,  Kuninori Kawabata

    发明人： Akira Kikutake ,  Masato Matsumiya ,  Satoshi Eto ,  Kuninori Kawabata

    IPC分类号： G11C700

    CPC分类号： G11C7/10

    摘要： It is one aspect of the present invention to split a common data bus established in common for a plurality of segments into a read-dedicated common data bus and a write dedicated common data bus, in a memory device comprising a plurality of segments each of which includes a plurality of memory cells. With such a constitution, write data can be supplied to the write data bus even when read data are present on the read common data bus due to a read operation; and even when operation frequencies increase, there are no limitations to the timing of write operations following reading and the speed of write operations following reading can be increased.

    摘要翻译： 本发明的一个方面是将在多个段中共同建立的公用数据总线分成读专用公用数据总线和写专用公用数据总线，在包括多个段的存储器件中， 包括多个存储单元。 通过这样的结构，即使读取的公共数据总线上的读取数据由于读取操作，也可以将写入数据提供给写入数据总线; 并且即使在操作频率增加的情况下，读取之后的写入操作的定时也没有限制，并且读取之后的写入操作的速度可以增加。

    Semiconductor integrated circuit
    32.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06201378B1

    公开(公告)日：2001-03-13

    申请号：US09301203

    申请日：1999-04-28

    申请人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

    发明人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

    IPC分类号： G05F316

    CPC分类号： G11C11/4074 ,  G11C5/147 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4099

    摘要： A semiconductor integrated circuit producing a given output voltage includes first and second operational amplifiers, and first and second transistors. The first and second operational amplifiers detect a voltage difference between a voltage applied to an input terminal and at least one reference voltage. The first and second transistors are turned ON or turned OFF according to the levels of voltages output from the first and second operational amplifiers. The first operational amplifier receives the output voltage at the input terminal. When the level of the output voltage becomes lower than the reference voltage, the first operational amplifier allows the first transistor to operate so as to raise the output voltage. In contrast, the second operational amplifier receives the output voltage at the input terminal. When the level of the output voltage exceeds the reference voltage, the second operational amplifier allows the second transistor to operate so as to lower the output voltage.

    摘要翻译： 产生给定输出电压的半导体集成电路包括第一和第二运算放大器以及第一和第二晶体管。 第一和第二运算放大器检测施加到输入端的电压与至少一个参考电压之间的电压差。 根据从第一和第二运算放大器输出的电压的电平，第一和第二晶体管导通或截止。 第一个运算放大器在输入端接收输出电压。 当输出电压的电平变得低于参考电压时，第一运算放大器允许第一晶体管工作，以便提高输出电压。 相反，第二运算放大器在输入端接收输出电压。 当输出电压的电平超过参考电压时，第二运算放大器允许第二晶体管工作，以降低输出电压。

    Semiconductor memory
    33.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US06188625B1

    公开(公告)日：2001-02-13

    申请号：US09461721

    申请日：1999-12-16

    申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Akira Kikutake

    发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Akira Kikutake

    IPC分类号： G11C1300

    CPC分类号： G11C11/4091

    摘要： For cutting off a path for flowing a read detection current from a high-potential power supply (Vii) of a read data bus amplifier (S/B 33) to the ground side of a read controller (41) via a sense amplifier (31) selected based on an address in a write to a memory cell, a semiconductor memory device have a logic circuit (42, 43) for calculating logic between a block select signal and a write status signal to change the potential at the read controller (41) to the same power supply potential as that at the S/B (33) when the write status signal is activated. This logic circuit can prevent any unwanted read detection current from flowing in a data write, so as to suppress current consumption in a write.

    摘要翻译： 为了切断用于将读取检测电流从读取数据总线放大器（S / B 33）的高电位电源（Vii）经由读出放大器（31）读取到读取控制器（41）的接地侧的路径 ），半导体存储器件具有用于计算块选择信号和写入状态信号之间的逻辑的逻辑电路（42,43），以改变读取控制器（41）处的电位 ）与写入状态信号被激活时，与S / B（33）的电源电位相同。 该逻辑电路可以防止任何不需要的读取检测电流在数据写入中流动，从而抑制写入中的电流消耗。

    Amplifier
    34.
    发明授权
    Amplifier 失效
    放大器

    公开(公告)号：US6140844A

    公开(公告)日：2000-10-31

    申请号：US55399

    申请日：1998-04-06

    申请人： Ayako Kitamoto ,  Masato Matsumiya

    发明人： Ayako Kitamoto ,  Masato Matsumiya

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/409 ,  G11C11/4091

    CPC分类号： G11C7/067 ,  G11C11/4091

    摘要： In a current sense amplifier for detecting and amplifying the difference between the currents flowing on a pair of signal lines, an active device is provided that works to limit the amplitude of an output node of the current sense amplifier. Further, a differential amplifier for amplifying the amplitude-limited output of the current sense amplifier is provided on the output side of the current sense amplifier.

    摘要翻译： 在用于检测和放大在一对信号线上流动的电流之间的差异的电流检测放大器中，提供了有效的器件，其用于限制电流检测放大器的输出节点的幅度。 此外，用于放大电流检测放大器的限幅输出的差分放大器设置在电流检测放大器的输出侧。

    Semiconductor memory device and data bus amplifier activation method for the semiconductor memory device
    35.
    发明授权
    Semiconductor memory device and data bus amplifier activation method for the semiconductor memory device 有权
    用于半导体存储器件的半导体存储器件和数据总线放大器激活方法

    公开(公告)号：US6130849A

    公开(公告)日：2000-10-10

    申请号：US300269

    申请日：1999-04-27

    申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Yuichi Uzawa ,  Toru Koga ,  Akira Kikutake

    发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Yuichi Uzawa ,  Toru Koga ,  Akira Kikutake

    IPC分类号： G11C11/413 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/02

    CPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229

    摘要： In a data bus amplifier activation method for a semiconductor memory device having a memory cell array, a column selection circuit for selecting a column in the memory cell array, a read data bus for transferring read data, output from the column selected by the column selection circuit, to a read data bus amplifier, and a write data bus for transferring write data, output from a write data bus amplifier, to the column selected by the column selection circuit, the read data bus amplifier or the write data bus amplifier is activated by detecting the selection of the column effected by the column selection circuit. By so doing, a read data bus amplifier enable signal or a write data bus amplifier enable signal can be generated after the occurrence of a column select signal, eliminating the need to allow a large margin for the generation timing of the read data bus amplifier enable signal or the write data bus amplifier enable signal, and as a result, the operating speed of the semiconductor memory device can be increased.

    摘要翻译： 在具有存储单元阵列的半导体存储器件的数据总线放大器激活方法中，用于选择存储单元阵列中的列的列选择电路，用于传送读数据的读数据总线，由列选择 电路，读取数据总线放大器以及用于将从数据总线放大器输出的写数据传送到由列选择电路选择的列的写数据总线，读数据总线放大器或写数据总线放大器被激活 通过检测由列选择电路实现的列的选择。 通过这样做，读数据总线放大器使能信号或写数据总线放大器使能信号可以在出现列选择信号之后产生，消除了对读数据总线放大器使能的产生定时的大余量 信号或写数据总线放大器使能信号，结果可以提高半导体存储器件的工作速度。

    Memory device having row decoder
    37.
    发明授权
    Memory device having row decoder 有权
    具有行解码器的存储器件

    公开(公告)号：US6111795A

    公开(公告)日：2000-08-29

    申请号：US342059

    申请日：1999-06-29

    申请人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

    发明人： Masato Takita ,  Masato Matsumiya ,  Masatomo Hasegawa ,  Toshimi Ikeda

    IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/00

    CPC分类号： G11C8/08 ,  G11C11/4076 ,  G11C11/4087 ,  G11C8/10 ,  G11C8/18

    摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

    摘要翻译： 一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。 另一方面，响应于激活命令的发出，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少定时 通过延迟电路20A将预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。 每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号 字解码器中的锁存电路。

    Semiconductor memory device having a precharge device
    39.
    发明授权
    Semiconductor memory device having a precharge device 失效
    具有预充电装置的半导体存储器件

    公开(公告)号：US06049493A

    公开(公告)日：2000-04-11

    申请号：US987618

    申请日：1997-12-09

    申请人： Ayako Kitamoto ,  Masato Matsumiya

    发明人： Ayako Kitamoto ,  Masato Matsumiya

    IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C2207/12

    摘要： During a precharging period, first a bit line is precharged to a first potential and a sense amplifier is precharged to a second potential. Then, the bit line and the sense amplifier are connected together thorough a bit line transfer gate, and the precharge potential at the bit line is set to a third potential in accordance with a ratio of their capacitances. Following this, a word line is rendered active to connect a memory cell to the bit line. In accordance with the potential in the memory cell, a minute voltage is generated to the bit line, and the sense amplifier detects the minute voltage and amplifies it. Since the first and the second potentials differ from each other, the third potential can be an intermediate potential nearer the first potential. For example, when the first potential is set to a ground potential and the second potential is set to one available at a high potential power source, the third potential is set to shift toward the ground potential from half the power source potential. Since this potential is higher than the ground potential, a potential which is higher or lower than the third potential by the equivalent of the minute voltage is generated at a selected bit line. The sense amplifier, therefore, can employ the third potential at the opposite bit line as a reference potential.

    摘要翻译： 在预充电期间，首先将位线预充电到第一电位，并将读出放大器预充电到第二电位。 然后，位线和读出放大器通过位线传输门连接在一起，并且根据它们的电容的比例将位线处的预充电电位设置为第三电位。 在此之后，字线被激活以将存储器单元连接到位线。 根据存储单元中的电位，对位线产生微小电压，读出放大器检测微小电压并放大。 由于第一和第二电位彼此不同，所以第三电位可以是接近第一电位的中间电位。 例如，当第一电位被设置为接地电位并且第二电位被设置为在高电位电源处可用的第一电位时，第三电位被设置为从电源电位的一半向接地电位移动。 由于该电位高于接地电位，所以在所选择的位线处产生相当于微小电压的高于或低于第三电位的电位。 因此，读出放大器可以在相对位线处使用第三电位作为参考电位。