中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

42 records (took 0.018 seconds)

    Variable-voltage CPU voltage regulator
    31.
    发明授权
    Variable-voltage CPU voltage regulator 失效
    可变电压CPU电压调节器

    公开(公告)号：US5919262A

    公开(公告)日：1999-07-06

    申请号：US17049

    申请日：1998-02-02

    Applicant: Dan Kikinis ,  Pascal Dornier

    Inventor： Dan Kikinis ,  Pascal Dornier

    IPC: H02M3/155 ,  G05F1/46 ,  G06F1/26

    CPC classification number: G05F1/465 ,  G06F1/26

    Abstract: An integrated CPU has an on-board switching voltage regulator with an electrically-erasable programmable read-only memory electronically accessible for storing a feedback reference coefficient for control. In further embodiments, output voltage is tuned via a second EEPROM storing an electronically accessible value in concert with a solid-state resistor ladder. In other embodiments, signals on interrupt lines to the CPU are monitored to provide a prewarning of impending activity by the CPU requiring dramatically increased current flow. In yet other embodiments, solid state circuitry is provided to reduce or eliminate capacitors used for dealing with input current surges to the CPU.

    Abstract translation: 集成CPU具有板载开关稳压器，其具有电可擦除可编程只读存储器，可电存取存储用于控制的反馈参考系数。 在另外的实施例中，输出电压通过存储与固态电阻梯一致的电子可访问值的第二EEPROM进行调谐。 在其他实施例中，监视到CPU的中断线上的信号被监视以提供CPU需要大大增加的电流的临时活动的预警。 在其他实施例中，提供固态电路以减少或消除用于处理CPU的输入电流浪涌的电容器。

    Structure and method for issuing interrupt requests as addresses and for decoding the addresses issued as interrupt requests
    33.
    发明授权
    Structure and method for issuing interrupt requests as addresses and for decoding the addresses issued as interrupt requests 失效
    发出中断请求作为地址和解码作为中断请求发出的地址的结构和方法

    公开(公告)号：US5805902A

    公开(公告)日：1998-09-08

    申请号：US967316

    申请日：1997-10-28

    Applicant: Dan Kikinis ,  Pascal Dornier

    Inventor： Dan Kikinis ,  Pascal Dornier

    IPC: F02B75/02 ,  G06F13/42 ,  G06F12/06 ,  G06F13/10 ,  G06F13/24

    CPC classification number: G06F13/423 ,  F02B2075/027

    Abstract: An interrupt control circuit for use in a computer system has a CPU, a peripheral I/O device, and a bus having address lines for carrying signals to and from the peripheral I/O device. Interrupt requests generated by the I/O device are encoded as address signals which are transmitted on the address bus lines. A predetermined set of addresses are set aside to represent the interrupt requests. The interrupt control circuit is coupled to the address bus lines to receive the encoded interrupt requests. The interrupt control circuit has an address decoder which receives address signals from the I/O device. When these address signals represent an address within the predetermined set of addresses set aside to represent the interrupt requests, the address decoder uses the address signals to create a plurality of interrupt control signals. The interrupt control signals are provided to an interrupt latch/decoder which uses the interrupt control signals to create interrupt request signals. The interrupt request signals are provided to an interrupt controller. In response, the interrupt controller and the CPU process the interrupt request.

    Abstract translation: 用于计算机系统的中断控制电路具有CPU，外围I / O设备和具有用于向外部I / O设备传送信号的地址线的总线。 由I / O设备生成的中断请求被编码为在地址总线上发送的地址信号。 放置预定的一组地址以表示中断请求。 中断控制电路耦合到地址总线以接收编码的中断请求。 中断控制电路具有从I / O设备接收地址信号的地址解码器。 当这些地址信号表示预定的一组地址，用于表示中断请求时，地址解码器使用地址信号来产生多个中断控制信号。 中断控制信号被提供给使用中断控制信号来产生中断请求信号的中断锁存/解码器。 中断请求信号提供给中断控制器。 作为响应，中断控制器和CPU处理中断请求。

    Timer-controlled computer system shutdown and startup
    35.
    发明授权
    Timer-controlled computer system shutdown and startup 失效

    公开(公告)号：US5542035A

    公开(公告)日：1996-07-30

    申请号：US143830

    申请日：1993-10-27

    Applicant: Dan Kikinis ,  Pascal Dornier

    Inventor： Dan Kikinis ,  Pascal Dornier

    IPC: G06F1/26 ,  G06F1/00 ,  G06F1/32 ,  G06F1/14

    CPC classification number: G06F1/3215 ,  G06F1/32 ,  G06F1/3203

    Abstract: A system for managing power levels for a general purpose computer having a standby and a full-power mode of operation provides apparatus and a method for monitoring times of user input and control routines for using the times of user input to calculate optimum times for initiating full power operation and standby mode. The control routines are configured to provide the optimum times to a real time clock that remains powered in the standby mode, which triggers switching elements to initiate full power and standby mode. In one embodiment of the system, startup and standby may be initiated either by user input or automatically by the power management system. Startup and standby initiation times may be different for different days and time periods based on both preprogrammed and calculated values.

    Timer-controlled computer system shutdown and startup
    36.
    发明授权
    Timer-controlled computer system shutdown and startup 失效
    定时器控制的计算机系统关机和启动

    公开(公告)号：US5920727A

    公开(公告)日：1999-07-06

    申请号：US908534

    申请日：1997-08-07

    Applicant: Dan Kikinis ,  Pascal Dornier

    Inventor： Dan Kikinis ,  Pascal Dornier

    IPC: G06F1/26 ,  G06F1/00 ,  G06F1/32 ,  G06F1/14

    CPC classification number: G06F1/3215 ,  G06F1/32 ,  G06F1/3203

    Abstract: A system for managing power levels for a general purpose computer having a standby and a full-power mode of operation provides apparatus and a method for monitoring times of user input and control routines for using the times of user input to calculate optimum times for initiating full power operation and standby mode. The control routines are configured to provide the optimum times to a real time clock that remains powered in the standby mode, which triggers switching elements to initiate full power and standby mode. In one embodiment of the system, startup and standby may be initiated either by user input or automatically by the power management system. Startup and standby initiation times may be different for different days and time periods based on both preprogrammed and calculated values.

    Abstract translation: 用于管理具有备用和全功率操作模式的通用计算机的功率水平的系统提供用于监视用户输入和控制例程的时间的装置和方法，以用于使用用户输入的时间来计算用于启动完全的最佳时间 电源运行和待机模式。 控制例程被配置为向待机模式下保持供电的实时时钟提供最佳时间，这触发开关元件启动全功率和待机模式。 在系统的一个实施例中，可以通过用户输入或由电力管理系统自动启动启动和备用。 基于预编程和计算值的不同日期和时间段的启动和待机启动时间可能不同。

    Micro personal digital assistant
    38.
    发明授权
    Micro personal digital assistant 失效
    微型个人数字助理

    公开(公告)号：US5708840A

    公开(公告)日：1998-01-13

    申请号：US610242

    申请日：1996-03-04

    Applicant: Dan Kikinis ,  Pascal Dornier ,  William J. Seiler

    Inventor： Dan Kikinis ,  Pascal Dornier ,  William J. Seiler

    IPC: G06F1/16 ,  G06F1/20 ,  G06F3/033 ,  G06F3/048 ,  G06F13/40 ,  G06F21/00 ,  H04M1/72 ,  H04M3/42 ,  H04N1/00 ,  H04N1/107 ,  H04N1/195 ,  H05K5/02 ,  G06F3/00

    CPC classification number: H05K5/0273 ,  G06F1/1616 ,  G06F1/1626 ,  G06F1/1632 ,  G06F1/203 ,  G06F13/409 ,  G06F21/62 ,  G06F3/0482 ,  H04N1/00127 ,  H04N1/00236 ,  H04N1/00241 ,  H04N1/00326 ,  H04N1/00331 ,  H04N1/00334 ,  H04N1/00339 ,  H04N1/00392 ,  H04N1/00411 ,  H01H2223/052 ,  H04M3/42323 ,  H04N1/00538 ,  H04N1/107 ,  H04N1/195 ,  H04N2201/0049 ,  H04N2201/0051 ,  H04N2201/0053 ,  H04N2201/0063

    Abstract: A personal digital assistant module with a local CPU, memory, and I/O interface has a host interface comprising a bus connected to the local CPU and a connector at a surface of the personal digital assistant for interfacing to a bus connector of a host general-purpose computer, providing direct bus communication between the personal digital assistant and the host general-purpose computer. In an embodiment, the personal digital assistant also has a means for storing a security code. The personal digital assistant according to the invention forms a host/satellite combination with a host computer having a docking bay, wherein upon docking a docking protocol controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In another embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port. Also disclosed are various embodiments for host systems compatible with personal digital assistants according to the invention, and a scanner system useful with displays of both personal digital assistants and hosts.

    Abstract translation: 具有本地CPU，存储器和I / O接口的个人数字助理模块具有包括连接到本地CPU的总线的主机接口和个人数字助理的表面处的连接器，用于与主机总线的总线连接器 提供个人数字助理和主机通用计算机之间的直接总线通信。 在一个实施例中，个人数字助理还具有用于存储安全码的装置。 根据本发明的个人数字助理与具有对接间隔的主计算机形成主机/卫星组合，其中在对接时，对接协议基于由个人数字助理提供的一个或多个密码来控制主机对个人数字助理的存储器的访问 用户到主机。 在另一个实施例中，个人数字助理还具有连接到本地CPU的扩展端口，并且扩展外围设备可以通过扩展端口连接和操作。 还公开了与根据本发明的个人数字助理兼容的主机系统的各种实施例，以及用于个人数字助理和主机的显示器的扫描器系统。

Patent Agency Ranking