公开(公告)号：US07037804B2

公开(公告)日：2006-05-02

申请号：US10695328

申请日：2003-10-27

Applicant: Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

Inventor： Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L25/50 ,  H01L21/185 ,  H01L21/743 ,  H01L21/76898 ,  H01L24/12 ,  H01L24/16 ,  H01L24/72 ,  H01L24/75 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/75315 ,  H01L2224/81203 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/0665 ,  H01L2924/00014

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.

Abstract translation: 三维（3-D）集成芯片系统设置有包括一个或多个集成电路（IC）装置的第一晶片; 包括一个或多个集成电路（IC）装置的第二晶片; 以及在指定位置沉积在第一和第二晶片的相对表面上的金属粘结层，以在第一和第二晶片上的有源IC器件之间建立电连接，并且当第一晶片为 使用柔性膀胱压力机压在第二晶片上，以考虑穿过第一和第二晶片的相对表面的金属粘合层的高度差异。

公开(公告)号：US07034394B2

公开(公告)日：2006-04-25

申请号：US10682137

申请日：2003-10-08

Applicant: Shriram Ramanathan ,  Sarah E. Kim ,  R. Scott List ,  Gregory M. Chrysler

Inventor： Shriram Ramanathan ,  Sarah E. Kim ,  R. Scott List ,  Gregory M. Chrysler

IPC: H01L23/34

CPC classification number: H01L35/32 ,  H01L23/38 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L27/16 ,  H01L2224/05001 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

公开(公告)号：US07537954B2

公开(公告)日：2009-05-26

申请号：US11298280

申请日：2005-12-09

Applicant: Shriram Ramanathan ,  Sarah E. Kim ,  R. Scott List ,  Gregory M. Chrysler

Inventor： Shriram Ramanathan ,  Sarah E. Kim ,  R. Scott List ,  Gregory M. Chrysler

IPC: H01L27/16 ,  H01L21/70

CPC classification number: H01L35/32 ,  H01L23/38 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L27/16 ,  H01L2224/05001 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

公开(公告)号：US07157787B2

公开(公告)日：2007-01-02

申请号：US10855032

申请日：2004-05-26

Applicant: Sarah E. Kim ,  R. Scott List ,  Scot A. Kellar

Inventor： Sarah E. Kim ,  R. Scott List ,  Scot A. Kellar

IPC: H01L29/40 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76831 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/81894 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83

Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

Abstract translation: 提供垂直堆叠晶片的方法以形成三维（3D）晶片堆叠。 这种方法包括：在相邻晶片的相对表面上选择性地沉积多条金属线; 通过金属线接合相邻的晶片，以在垂直堆叠的晶片上的有源器件之间建立电连接; 以及形成一个或多个通孔以在垂直堆叠的晶片上的有源器件和外部互连之间建立电连接。 通过使用一个或多个虚拟通孔，锥形通孔或并入现有的铜（Cu）双镶嵌工艺，可以增加相邻晶片的相对表面上的金属结合区域。

公开(公告)号：US07148565B2

公开(公告)日：2006-12-12

申请号：US10443831

申请日：2003-05-23

Applicant: Sarah E. Kim ,  R. Scott List ,  Tom Letson

Inventor： Sarah E. Kim ,  R. Scott List ,  Tom Letson

IPC: H01L23/04 ,  H01L23/02

CPC classification number: H01L21/30604 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107

Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.

公开(公告)号：US07120817B2

公开(公告)日：2006-10-10

申请号：US10447706

申请日：2003-05-29

Applicant: Mauro J. Kobrinsky ,  Sourav Chakravarty ,  R. Scott List

Inventor： Mauro J. Kobrinsky ,  Sourav Chakravarty ,  R. Scott List

IPC: G06F1/04

CPC classification number: G06F1/10

Abstract: A closed-loop based timing signal distribution architecture includes at least one signal source coupled to a signal path disposed in a closed loop arrangement to facilitate generation of a standing wave signal within the signal path. In one embodiment, at least one receiver is coupled to the signal path to generate at least one digital clock signal based upon the standing wave signal.

Abstract translation: 基于闭环的定时信号分配架构包括耦合到以闭环布置设置的信号路径的至少一个信号源，以便于在信号路径内产生驻波信号。 在一个实施例中，至少一个接收器耦合到信号路径，以基于驻波信号产生至少一个数字时钟信号。

公开(公告)号：US20050104199A1

公开(公告)日：2005-05-19

申请号：US11012519

申请日：2004-12-15

Applicant: R. Scott List ,  Alan Myers ,  Quat Vu

Inventor： R. Scott List ,  Alan Myers ,  Quat Vu

IPC: F04B17/00 ,  F04B19/00 ,  F24D3/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/34

CPC classification number: F04B17/00 ,  F04B19/006

Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.

Abstract translation: 可以使用具有纳米多孔开孔电介质玻璃料的半导体加工技术制造电渗泵。 这种玻璃料可能导致具有更好泵送能力的电渗泵。

公开(公告)号：US06790780B2

公开(公告)日：2004-09-14

申请号：US09965972

申请日：2001-09-27

Applicant: Sarah E. Kim ,  R. Scott List ,  Bruce A. Block

Inventor： Sarah E. Kim ,  R. Scott List ,  Bruce A. Block

IPC: H01L21302

CPC classification number: H01L21/311 ,  H01L21/302 ,  H01L21/76807 ,  H01L21/76877 ,  H01L28/55 ,  H01L28/75

Abstract: A three dimensional capacitor fabricated as part of a dual damascene process is disclosed. The capacitor structure comprises two barrier metal layers separated by a high k dielectric and is formed in all the via and trench openings. The upper barrier layer and dielectric is selectively removed from those openings which will have ordinary vias and conductors, the other opening remains as capaitor.

Abstract translation: 公开了作为双镶嵌工艺的一部分制造的三维电容器。 电容器结构包括由高k电介质隔开的两个阻挡金属层，并且形成在所有通孔和沟槽开口中。 从具有普通通孔和导体的那些开口选择性地去除上阻挡层和电介质，另一个开口保持为电容器。

公开(公告)号：US06762076B2

公开(公告)日：2004-07-13

申请号：US10077967

申请日：2002-02-20

Applicant: Sarah E. Kim ,  R. Scott List ,  Scot A. Kellar

Inventor： Sarah E. Kim ,  R. Scott List ,  Scot A. Kellar

IPC: H01L2144

CPC classification number: H01L21/76831 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/81894 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83

Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

公开(公告)号：US06645832B2

公开(公告)日：2003-11-11

申请号：US10077822

申请日：2002-02-20

Applicant: Sarah E. Kim ,  R. Scott List ,  Tom Letson

Inventor： Sarah E. Kim ,  R. Scott List ,  Tom Letson

IPC: H01L2144

CPC classification number: H01L21/30604 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107

Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.