公开(公告)号：US07667319B2

公开(公告)日：2010-02-23

申请号：US11012519

申请日：2004-12-15

Applicant: R. Scott List ,  Alan Myers ,  Quat T. Vu

Inventor： R. Scott List ,  Alan Myers ,  Quat T. Vu

IPC: H01L23/34

CPC classification number: F04B17/00 ,  F04B19/006

Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.

Abstract translation: 可以使用具有纳米多孔开孔电介质玻璃料的半导体加工技术制造电渗泵。 这种玻璃料可能导致具有更好泵送能力的电渗泵。

公开(公告)号：US07300871B2

公开(公告)日：2007-11-27

申请号：US10984604

申请日：2004-11-08

Applicant: Stefan Hau-Riege ,  R. Scott List

Inventor： Stefan Hau-Riege ,  R. Scott List

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.

Abstract translation: 描述制造半导体器件的方法。 该方法包括形成接触通孔的导电层，使得导电层在远离通孔的地方包括较高浓度的通孔附近的掺杂剂的电迁移量。

公开(公告)号：US07129172B2

公开(公告)日：2006-10-31

申请号：US10811758

申请日：2004-03-29

Applicant: Patrick Morrow ,  R. Scott List ,  Michael Y. Chan

Inventor： Patrick Morrow ,  R. Scott List ,  Michael Y. Chan

IPC: H01L21/302

CPC classification number: H01L21/304 ,  H01L21/187 ,  Y10S438/977

Abstract: According to one embodiment a method is disclosed. The method includes applying a photoresist layer to a first wafer, etching the first wafer, bonding the first wafer to a second wafer and thinning the first wafer; wherein an unsupported bevel portion of the first wafer is removed.

Abstract translation: 根据一个实施例，公开了一种方法。 该方法包括将光致抗蚀剂层施加到第一晶片，蚀刻第一晶片，将第一晶片接合到第二晶片并使第一晶片变薄; 其中去除第一晶片的未支撑的斜面部分。

公开(公告)号：US07105382B2

公开(公告)日：2006-09-12

申请号：US10721441

申请日：2003-11-24

Applicant: Alan M. Myers ,  Sarah E. Kim ,  R. Scott List

Inventor： Alan M. Myers ,  Sarah E. Kim ,  R. Scott List

IPC: H01L21/50

CPC classification number: H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/00

Abstract: A device where the electrodes of an electroosmotic pump are located directly in the flow-producing region of the electroosmotic pump is described as well as methods of forming such a device. Placing the electrodes of an electroosmotic pump directly in the flow-producing region of the electroosmotic pump may increase the flow rate of a cooling fluid that is pumped through the pump. The cooling fluid may then remove a greater amount of heat from the substrate over which it is flowed. The substrate may be the non-device side of a die or a thermal management chip that is placed in direct contact with the non-device side of a die. In these instances the electroosmotic pump may be part of a microelectronic package containing the die or the thermal management chip.

Abstract translation: 描述电渗泵的电极直接位于电渗泵的流动产生区域中的装置以及形成这种装置的方法。 将电渗泵的电极直接放置在电渗泵的流动产生区域中可以增加泵送通过泵的冷却流体的流量。 然后，冷却流体可以从其流过的基底上移除更大量的热量。 衬底可以是与管芯的非器件侧直接接触的管芯或热管理芯片的非器件侧。 在这些情况下，电渗泵可以是包含管芯或热管理芯片的微电子封装的一部分。

公开(公告)号：US07056807B2

公开(公告)日：2006-06-06

申请号：US10613006

申请日：2003-07-07

Applicant: Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

Inventor： Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

IPC: H01L21/301

CPC classification number: H01L24/10 ,  H01L23/481 ,  H01L23/585 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/2919 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.

公开(公告)号：US06908565B2

公开(公告)日：2005-06-21

申请号：US10328958

申请日：2002-12-24

Applicant: Sarah E. Kim ,  R. Scott List

Inventor： Sarah E. Kim ,  R. Scott List

IPC: H01L21/20 ,  H01L21/306 ,  H01L25/065 ,  H01L21/00

CPC classification number: H01L25/0657 ,  H01L21/2007 ,  H01L21/30604 ,  H01L21/30608 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include etching away unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.

Abstract translation: 在堆叠的微电子器件的制造中，用于薄化晶片到晶片垂直叠层的方法。 所述方法包括蚀刻在垂直叠层中待薄化的晶片的未支撑部分。 未支撑部分的去除基本上消除了晶片的潜在的破裂和碎裂，当存在未支撑的部分时，这可能在稀化过程中发生。

公开(公告)号：US06887769B2

公开(公告)日：2005-05-03

申请号：US10066645

申请日：2002-02-06

Applicant: Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

Inventor： Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

IPC: H01L21/30 ,  H01L21/302 ,  H01L21/46 ,  H01L21/461 ,  H01L21/60 ,  H01L21/98 ,  H01L23/48 ,  H01L23/485 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L23/481 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/2919 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.

Abstract translation: 三维（3-D）集成芯片系统具有包括一个或多个集成电路（IC）装置的第一晶片; 包括一个或多个集成电路（IC）装置的第二晶片; 以及在指定位置处沉积在第一和第二晶片的相对表面上的金属线，其中包围金属线的层间电介质（ILD）凹槽以促进第一和第二晶片之间的直接金属接合，并建立第一和第二晶片上的有源IC器件之间的电连接 和第二晶片。

公开(公告)号：US06790748B2

公开(公告)日：2004-09-14

申请号：US10326206

申请日：2002-12-19

Applicant: Sarah E. Kim ,  R. Scott List ,  Mauro J. Kobrinsky

Inventor： Sarah E. Kim ,  R. Scott List ,  Mauro J. Kobrinsky

IPC: H01L2176

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L23/481 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/15311 ,  Y10S438/977 ,  H01L2924/014 ,  H01L2224/05599

Abstract: Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include physically removing unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.

Abstract translation: 在堆叠的微电子器件的制造中，用于薄化晶片到晶片垂直叠层的方法。 这些方法包括在垂直堆叠中物理去除待稀释的晶片的未支撑部分。 未支撑部分的去除基本上消除了晶片的潜在的破裂和碎裂，当存在未支撑的部分时，这可能在稀化过程中发生。

公开(公告)号：US07696015B2

公开(公告)日：2010-04-13

申请号：US11448232

申请日：2006-06-07

Applicant: Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

Inventor： Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

IPC: H01L21/20 ,  H01L21/48 ,  H01L21/44

CPC classification number: F04B17/00 ,  F04B19/006 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06589 ,  H01L2924/01322

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract translation: 一组发热集成电路芯片可以设置有中间冷却集成电路芯片。 冷却集成电路芯片可以包括用于冷却流体流动的微通道。 可以使用集成的电渗泵泵送冷却流体。 在一些实施方案中，使用集成的重组合器可以实现冷却流体气体的去除。

公开(公告)号：US07615462B2

公开(公告)日：2009-11-10

申请号：US11528986

申请日：2006-09-27

Applicant: Sarah E. Kim ,  R. Scott List ,  Tom Letson

Inventor： Sarah E. Kim ,  R. Scott List ,  Tom Letson

IPC: H01L21/30 ,  H01L21/44

CPC classification number: H01L21/30604 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107

Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.

Abstract translation: 在垂直堆叠的晶片中形成硅（Si）通孔的方法设置有从顶部晶片的选定金属线和在接触插塞之前形成的蚀刻停止层延伸的接触插塞。 这种方法包括选择性地蚀刻通过顶部晶片的硅（Si），直到被蚀刻停止层阻止以形成Si通孔; 沉积氧化物层以使Si通孔的侧壁绝缘; 在氧化物层和Si通孔的底部形成阻挡层; 以及将导电金属沉积到Si通孔中以提供位于垂直堆叠的晶片上的有源IC器件与外部互连之间的电连接。