公开(公告)号：US11056379B2

公开(公告)日：2021-07-06

申请号：US14925715

申请日：2015-10-28

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Anthony Barker ,  Huma Ashraf ,  Brian Kiernan

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/3065 ,  H01J37/32

Abstract: A clamp assembly is for clamping an outer peripheral portion of a substrate to a support in a plasma processing chamber. An RF bias power is applied to the support during the plasma processing of the substrate. The clamp assembly includes an outer clamp member, and an inner clamp member which is received by the outer clamp member, the inner clamp member defining an aperture which exposes the substrate to the plasma processing. The outer clamp member has an inner portion terminating in an inner edge, wherein the inner portion is spaced apart from the inner clamp member.

公开(公告)号：US20210175122A1

公开(公告)日：2021-06-10

申请号：US17093597

申请日：2020-11-09

Applicant: SPTS Technologies Limited

Inventor： Martin Hanicinec ,  Janet Hopkins ,  Oliver Ansell

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/67

Abstract: A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies, each die comprising one integrated circuit. The process comprises: disposing a coating upon the wafer; removing at least a portion of the coating to expose regions of the wafer, along which the wafer is to be diced, to form a workpiece; disposing the workpiece upon a platen within a processing chamber; plasma treating the workpiece with a set of plasma treatment conditions to etch a portion of the exposed regions of the wafer to form a wafer groove which extends laterally beneath the coating to form an undercut; and plasma etching the workpiece with a set of plasma etch conditions, which are different to the plasma treatment conditions, to etch through the wafer and dice the wafer along the wafer groove.

公开(公告)号：US20210175082A1

公开(公告)日：2021-06-10

申请号：US17098404

申请日：2020-11-15

Applicant: SPTS Technologies Limited

Inventor： Huma Ashraf ,  Alex Croot ,  Kevin Riddell

IPC: H01L21/04 ,  H01L21/67 ,  H01L21/033

Abstract: A substrate with a mask formed thereon is provided. The substrate is formed from a compound semiconductor material. A first plasma etch step is performed to anisotropically etch the substrate through the opening to produce a partially formed feature having a bottom surface comprising a peripheral region. A second plasma etch step is performed to anisotropically etch the bottom surface of the partially formed feature through the opening while depositing a passivation material onto the mask so as to reduce a dimension of the opening. The reduction of the dimension of the opening causes an attenuation in etching of the peripheral region thereby producing a fully formed feature having a bottom surface comprising a central region and an edge region. The central region is deeper than the edge region of the bottom surface of the fully formed feature.

公开(公告)号：US10900114B2

公开(公告)日：2021-01-26

申请号：US15084574

申请日：2016-03-30

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Stephen R Burgess ,  Rhonda Hyndman ,  Amit Rastogi ,  Eduardo Paulo Lima ,  Clive L Widdicks ,  Paul Rich ,  Scott Haymore ,  Daniel Cook

IPC: C23C14/06 ,  C23C14/10 ,  C23C14/34 ,  C23C14/35 ,  H01J37/34 ,  H01J37/32

Abstract: A method is for depositing a dielectric material on to a substrate in a chamber by pulsed DC magnetron sputtering with a pulsed DC magnetron device which produces one or more primary magnetic fields. In the method, a sputtering material is sputtered from a target, wherein the target and the substrate are separated by a gap in the range 2.5 to 10 cm and a secondary magnetic field is produced within the chamber which causes a plasma produced by the pulsed DC magnetron device to expand towards one or more walls of the chamber.

公开(公告)号：US20210005439A1

公开(公告)日：2021-01-07

申请号：US16918202

申请日：2020-07-01

Applicant: SPTS Technologies Limited

Inventor： Rhonda Hyndman ,  Steve Burgess

IPC: H01J37/34 ,  C23C14/50 ,  C23C14/35

Abstract: A magnetron sputtering apparatus for depositing material onto a substrate, comprises: a chamber comprising a substrate support and a target; a plasma production device configured to produce a plasma within the chamber suitable for sputtering material from the target onto the substrate; and a thermally conductive grid comprising a plurality of cells. Each cell comprises an aperture and the ratio of the height of the cells to the width of the apertures is less than 1.0. The grid is disposed between the substrate support and the target and is substantially parallel to the target. The upper surface of the substrate support is positioned at a distance of 75 mm or less from the lower surface of the target.

公开(公告)号：US10812035B2

公开(公告)日：2020-10-20

申请号：US16129346

申请日：2018-09-12

Applicant: SPTS Technologies Limited

Inventor： Rhonda Hyndman ,  Steve Burgess

IPC: H03H3/10 ,  H03H9/25 ,  C23C14/08 ,  C23C14/34 ,  C23C14/35 ,  H03H9/02 ,  H03H9/145 ,  H03H9/64 ,  H01L41/053 ,  H01L41/23 ,  C23C14/10 ,  C23C14/54 ,  H03H3/08 ,  C23C14/00 ,  H03H3/04

Abstract: A method of reducing non-uniformity in the resonance frequencies of a surface acoustic wave (SAW) device, the SAW device comprising a silicon oxide layer comprising an oxide of silicon deposited over interdigital transducers on a piezoelectric substrate by reactive sputtering. The method comprises positioning a piezoelectric substrate having interdigital transducers on a substrate support, then depositing a silicon oxide layer comprising an oxide of silicon over the piezoelectric substrate and the interdigital transducers to form a SAW device. The substrate support is positioned relative to a sputtering target so that the silicon oxide layer of the SAW device has an arithmetic mean surface roughness (Ra) of 11 angstroms or less.

公开(公告)号：US20200058498A1

公开(公告)日：2020-02-20

申请号：US16541615

申请日：2019-08-15

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Katherine Crook ,  Steve Burgess

IPC: H01L21/02 ,  H01J37/32 ,  C23C16/505 ,  C23C16/34

Abstract: A method is for depositing silicon nitride by plasma-enhanced chemical vapour deposition (PECVD). The method includes providing a PECVD apparatus including a chamber and a substrate support disposed within the chamber, positioning a substrate on the substrate support, introducing a nitrogen gas (N2) precursor into the chamber, applying a high frequency (HF) RF power and a low frequency (LF) RF power to sustain a plasma in the chamber, introducing a silane precursor into the chamber while the HF and LF RF powers are being applied so that the silane precursor forms part of the plasma being sustained, and subsequently removing the LF RF power or reducing the LF RF power by at least 90% while continuing to sustain the plasma so that silicon nitride is deposited onto the substrate by PECVD.

公开(公告)号：US20190338414A1

公开(公告)日：2019-11-07

申请号：US15968433

申请日：2018-05-01

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： MICHAEL GRIMES ,  YUYUAN LIN

IPC: C23C16/02 ,  H05K3/28 ,  C23C16/40 ,  B05D1/00 ,  C23C16/455 ,  C23C16/44

Abstract: A method of forming a passivation layer on a substrate includes providing a substrate in a processing chamber. The substrate includes a metallic surface which is a copper, tin or silver surface, or an alloyed surface of one or more of copper, tin or silver. The method further includes depositing at least one organic layer onto the metallic surface by vapour deposition, the organic layer formed from an organic precursor. The organic precursor includes a first functional group including at least one of oxygen, nitrogen, phosphorus, sulphur, selenium, tellurium, or silicon, and a second functional group selected from hydroxyl (—OH) or carboxyl (—COOH). The first functional group is adsorbed onto the metallic surface. The method further includes depositing at least one inorganic layer onto the organic layer by vapour deposition, wherein the second functional group acts as an attachment site for the inorganic layer.

公开(公告)号：US10446374B2

公开(公告)日：2019-10-15

申请号：US15446052

申请日：2017-03-01

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Paul Bennett

IPC: H01J37/32 ,  B08B7/00 ,  B08B9/08 ,  C23C16/44 ,  C23C16/448 ,  C23C16/503 ,  C23C16/505 ,  H01L21/67

Abstract: A plasma processing apparatus for plasma processing a substrate comprising includes a chamber having one or more walls, in which a portion of the walls of the chamber is an electrode structure formed from a metallic material and configured to act as a primary winding of an inductively coupled plasma source, and an electrical signal supply device for supplying an electrical signal that drives the electrode structure as a primary winding of an inductively coupled plasma source to sustain an inductively coupled plasma within the chamber.

公开(公告)号：US20180350615A1

公开(公告)日：2018-12-06

申请号：US15995184

申请日：2018-06-01

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Oliver J. ANSELL ,  Martin HANICINEC ,  Janet HOPKINS

IPC: H01L21/3065 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L21/78

Abstract: A method is for plasma etching one or more dicing lanes in a silicon substrate having a backside metal layer attached thereto. The method includes performing a main etch using a cyclical plasma etch process in which a deposition step and an etch step are alternately repeated to produce dicing lanes having scalloped sidewalls, and switching to performing a secondary etch using a cyclical plasma etch process in which a deposition step and an etch step are alternately repeated until the backside metal layer is reached. The amount of silicon removed in one etch step during the secondary etch is half or less than half of the amount of silicon removed in one etch step during the main etch.