公开(公告)号：US08456888B2

公开(公告)日：2013-06-04

申请号：US12899912

申请日：2010-10-07

Applicant: Seung Hyun Lee

Inventor： Seung Hyun Lee

IPC: G11C11/00

CPC classification number: H01L27/2463 ,  H01L27/222 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

Abstract: A semiconductor memory device with a variable resistance element includes a plurality of active areas isolated from one another by an isolation layer formed in a substrate, a plurality of word lines crossing over the plurality of active areas, an auxiliary source line disposed between two selected word lines and commonly connected to at least two active areas among the plurality of active areas between the two selected word lines, and a plurality of contact plugs each connected to a corresponding active area.

Abstract translation: 具有可变电阻元件的半导体存储器件包括通过形成在衬底中的隔离层彼此隔离的多个有源区域，跨越多个有源区域的多个字线，设置在两个选择字之间的辅助源极线 并且通常连接到两个所选字线之间的多个有效区域中的至少两个有效区域，以及各自连接到相应的有效区域的多个接触插塞。

公开(公告)号：US20130069226A1

公开(公告)日：2013-03-21

申请号：US13337197

申请日：2011-12-26

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor package includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first connection members on the first surface; a second structural body placed over the first structural body, and formed with second connection members on a surface thereof which faces the first surface of the first structural body; and an interposer interposed between the first structural body and the second structural body, and having a body which is formed with openings into which the first connection members and the second connection members are inserted and a conductive layer which is formed to fill the openings.

Abstract translation: 半导体封装包括具有第一表面的第一结构体和远离所述第一表面的第二表面，并且在所述第一表面上形成有第一连接构件; 第二结构体，其放置在第一结构体上，并且在与第一结构体的第一表面相对的表面上形成有第二连接构件; 以及介于所述第一结构体和所述第二结构体之间的插入体，并且具有形成有所述第一连接构件和所述第二连接构件插入的开口的主体和形成为填充所述开口的导电层。

公开(公告)号：US20120299199A1

公开(公告)日：2012-11-29

申请号：US13569562

申请日：2012-08-08

Applicant: Jong Hoon KIM ,  Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Tae Min KANG

Inventor： Jong Hoon KIM ,  Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Tae Min KANG

IPC: H01L23/488

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

公开(公告)号：US20120295376A1

公开(公告)日：2012-11-22

申请号：US13473300

申请日：2012-05-16

Applicant: Keon Jae LEE ,  So Young PARK ,  Seung Hyun LEE ,  Kwi Il PARK ,  Min KOO

Inventor： Keon Jae LEE ,  So Young PARK ,  Seung Hyun LEE ,  Kwi Il PARK ,  Min KOO

IPC: H01L33/30 ,  H01L33/08

CPC classification number: H01L25/0753 ,  A61N5/0622 ,  A61N2005/0652 ,  A61N2005/0662 ,  H01L24/19 ,  H01L33/62 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Disclosed are a method for fabricating a GaN LED array device for optogenetics and a GaN LED array device fabricated thereby.

Abstract translation: 公开了一种用于制造用于光遗传学的GaN LED阵列器件和由其制造的GaN LED阵列器件的方法。

公开(公告)号：US20120241828A1

公开(公告)日：2012-09-27

申请号：US13336069

申请日：2011-12-23

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: H01L29/82 ,  H01L21/8246

CPC classification number: H01L43/12 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607 ,  H01L27/226 ,  H01L27/228 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08

Abstract: A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.

Abstract translation: 一种制造半导体存储器件的方法包括在下电极上形成磁性隧道结层，在磁性隧道结层上形成具有环形形状的间隔物，在环形间隔物的两个侧壁表面上形成上电极， ，并通过使用上电极作为蚀刻掩模蚀刻磁性隧道结层。

公开(公告)号：US08154010B2

公开(公告)日：2012-04-10

申请号：US12318502

申请日：2008-12-30

Applicant: Seung-Hyun Lee

Inventor： Seung-Hyun Lee

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  H01L27/285 ,  H01L51/0583 ,  Y10S977/742 ,  Y10S977/762

Abstract: A memory device includes a first electrode, a second electrode spaced apart from the first electrode and a nanotube or nanowire network disposed between the first electrode and the second electrode, having a stacked structure of a P-type network and an N-type network, and having a diode characteristic. Since the nanotube or nanowire network has the stacked structure of the P-type network and the N-type network, and has the diode characteristic, it is possible to enhance a degree of integration of the memory device and simplify the fabrication processes without separately requiring a selection device.

Abstract translation: 存储器件包括第一电极，与第一电极间隔开的第二电极和设置在第一电极和第二电极之间的纳米管或纳米线网络，具有P型网络和N型网络的堆叠结构， 并具有二极管特性。 由于纳米管或纳米线网络具有P型网络和N型网络的堆叠结构，并且具有二极管特性，因此可以提高存储器件的集成度并简化制造工艺，而无需单独要求 选择装置。

公开(公告)号：US20110268069A1

公开(公告)日：2011-11-03

申请号：US13142773

申请日：2009-12-24

Applicant: Kuk-Jin Song ,  Seung-Hyun Lee

Inventor： Kuk-Jin Song ,  Seung-Hyun Lee

IPC: H04W72/04

CPC classification number: H04W72/1231 ,  H04W52/146 ,  H04W52/228 ,  H04W52/262 ,  H04W72/1289

Abstract: The present invention relates to an apparatus and a method for scheduling multiple bursts containing a collaborative spatial multiplexing (CSM) burst and a non-CSM burst in a broadband radio communication system. The method comprises the steps of packet-scheduling an uplink data packet corresponding to the bandwidth request from a terminal such that the packet is allocated to either the CSM burst or the non-CSM burst, determining a modulation and coding scheme (MCS) level and a transmission power level corresponding to the packet-scheduled uplink data packet using the maximum number of bytes for each MCS level in accordance with the types of the multiple bursts calculated for the terminal, determining a transmission power offset in accordance with the type of the burst to which the packet-scheduled uplink data packet is allocated using the MCS level and the power transmission level determined in the previous step, and generating MAP information for the terminal, containing burst allocation information of the uplink data packet and information of the transmission power offset determined in the previous step.

Abstract translation: 本发明涉及一种用于在宽带无线电通信系统中调度包含协作空间复用（CSM）突发和非CSM突发的多个突发的装置和方法。 该方法包括以下步骤：从终端分组调度对应于带宽请求的上行链路数据分组，使得分组被分配给CSM突发或非CSM突发，确定调制和编码方案（MCS）级别;以及 根据针对终端计算的多个突发的类型，使用针对每个MCS级别的最大字节数对应于分组调度的上行链路数据分组的发送功率电平，根据突发的类型确定发送功率偏移 使用在上一步骤中确定的MCS级别和功率传输级别来分配分组预定的上行链路数据分组，并且生成包含上行链路数据分组的突发分配信息和发送功率偏移的信息的终端的MAP信息 在上一步确定。

公开(公告)号：US08049341B2

公开(公告)日：2011-11-01

申请号：US12244322

申请日：2008-10-02

Applicant: Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

Inventor： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

IPC: H01L23/52

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

Abstract translation: 本发明提供一种叠层半导体封装及其制造方法，其具有降低的电阻和增加的接合力。 半导体封装包括彼此堆叠的至少两个半导体芯片。 每个半导体芯片具有形成在上表面上并具有通孔的多个接合焊盘。 第一布线位于半导体芯片的上表面上，位于通孔的表面上，分别连接到它们各自的接合焊盘上。 第二布线位于半导体芯片的下表面和连接到它们各自的第一布线的相应通孔的表面上。 半导体芯片被堆叠，使得位于向上定位的半导体芯片的上表面上的第一布线分别与形成在向下定位的半导体芯片的下表面上的相应的第二布线接合。

公开(公告)号：US20110127611A1

公开(公告)日：2011-06-02

申请号：US12842598

申请日：2010-07-23

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device comprises an active region having an upper portion and a sidewall portion which are protruded from the top surface of a device isolation region, and a silicide film disposed in the upper portion and the sidewall portion of the active region, thereby effectively reducing resistance in a source/drain region of the semiconductor device. As a result, the entire resistance of the semiconductor device comprising a fin-type gate can be reduced to improve characteristics of the semiconductor device.

Abstract translation: 半导体器件包括具有从器件隔离区的顶表面突出的上部和侧壁部分的有源区和设置在有源区的上部和侧壁部分中的硅化物膜，从而有效地降低电阻 在半导体器件的源/漏区中。 结果，可以减少包括鳍型栅极的半导体器件的整个电阻，以改善半导体器件的特性。

公开(公告)号：US20110041022A1

公开(公告)日：2011-02-17

申请号：US12857162

申请日：2010-08-16

Applicant: Jae-Hong Park ,  Seung-Hyun Lee ,  Jin-Young Oh ,  Dong-Jun Kang

Inventor： Jae-Hong Park ,  Seung-Hyun Lee ,  Jin-Young Oh ,  Dong-Jun Kang

IPC: H04L1/18 ,  G06F11/14

CPC classification number: H04L1/1854 ,  H04L1/1841 ,  H04L1/1848

Abstract: An apparatus and a method for operating an Automatic Repeat reQuest (ARQ) in consideration of an operation state of a Hybrid Automatic Repeat reQuest (HARQ) in a wireless communication system. In the method, when an an ARQ timer expires, operation state information of a HARQ module for controlling a HARQ is determined. Whether to delay generation of Negative ACKnowledge (NACK) information in consideration of the operation state information of the HARQ module, then determined. When determining to delay the generation of the NACK information, the generation of the NACK information is delayed for a delay time determined in consideration of the operation state information of the HARQ module.

Abstract translation: 考虑到无线通信系统中的混合自动重传请求（HARQ）的操作状态来操作自动重复请求（ARQ）的装置和方法。 在该方法中，当ARQ定时器期满时，确定用于控制HARQ的HARQ模块的操作状态信息。 考虑到HARQ模块的运行状态信息，是否延迟生成负值确认（NACK）信息，然后确定。 当确定延迟生成NACK信息时，NACK信息的生成被延迟考虑到HARQ模块的操作状态信息确定的延迟时间。