公开(公告)号：US08238325B2

公开(公告)日：2012-08-07

申请号：US10589990

申请日：2005-10-25

Applicant: Kazuhiro Hayakawa ,  Satoru Yoshida ,  Makoto Fukuda ,  Nobuo Shigeta ,  Kazuhiko Ogawa ,  Shin Hashimoto

Inventor： Kazuhiro Hayakawa ,  Satoru Yoshida ,  Makoto Fukuda ,  Nobuo Shigeta ,  Kazuhiko Ogawa ,  Shin Hashimoto

IPC: H04L12/66

CPC classification number: H04J14/0227 ,  H04J14/0241 ,  H04J14/0284 ,  H04L12/56 ,  H04Q11/0062 ,  H04Q11/0066 ,  H04Q11/0071 ,  H04Q2011/0098

Abstract: Full-mesh WDM transmission units, each of which includes n number of interfaces and is capable of establishing a bidirectional full-mesh communication between all of the interfaces using wavelength paths based on a wavelength division multiplexing technique, are connected in a multistage tree-shaped structure by internetwork connection units through edge-packet transfer units connected to the respective interfaces. Therefore, it is possible to hold a direct communication between user terminals connected to the edge-packet transfer units of the same full-mesh WDM transmission unit, and to realize scalability by a multistage connection configuration.

Abstract translation: 全网WDM传输单元，其中每个包括n个接口，并且能够使用基于波分复用技术的波长路径在所有接口之间建立双向全网状通信，以多级树状 通过互连网络连接单元通过连接到相应接口的边缘分组传送单元进行结构化。 因此，可以在连接到同一全网WDM传输单元的边缘分组传送单元的用户终端之间进行直接通信，并且通过多级连接配置来实现可扩展性。

公开(公告)号：US08148751B2

公开(公告)日：2012-04-03

申请号：US12732775

申请日：2010-03-26

Applicant: Shin Hashimoto ,  Tatsuya Tanabe ,  Katsushi Akita ,  Hideaki Nakahata ,  Hiroshi Amano

Inventor： Shin Hashimoto ,  Tatsuya Tanabe ,  Katsushi Akita ,  Hideaki Nakahata ,  Hiroshi Amano

IPC: H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/2003 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/872

Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1-XN (0

Abstract translation: 提供III族氮化物半导体器件和III族氮化物半导体晶片。 III族氮化物半导体器件具有包含含有Al的III族氮化物基半导体的沟道层。 III族氮化物半导体器件可以增强二维电子气的迁移率并改善电流特性。 III族氮化物半导体晶片用于制造III族氮化物半导体器件。 III族氮化物半导体晶片包括由Al x Ga 1-x N（0

公开(公告)号：US20120006263A1

公开(公告)日：2012-01-12

申请号：US12999973

申请日：2009-08-06

Applicant: Shin Hashimoto ,  Tatsuya Tanabe

Inventor： Shin Hashimoto ,  Tatsuya Tanabe

IPC: B05C9/14 ,  H01L21/00 ,  C23C16/34 ,  B05C11/00 ,  C23C16/46

CPC classification number: C23C16/46 ,  C30B25/10 ,  C30B25/16 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262

Abstract: When a film is to be deposited on a semiconductor substrate or the like in a heating ambient, the semiconductor substrate is caused to warp (curve) to a considerable extent merely due to an increased temperature. The warpage leads to problems such as degradation of the homogeneity of the quality of the film deposited on the substrate and a high possibility of generation of a crack in the substrate. Accordingly, a film deposition apparatus of the present invention heats the substrate both from above and from below a main surface of the substrate so that a temperature gradient (temperature difference) between the upper side and the lower side of the main surface is reduced and the warpage of the substrate is suppressed. More preferably a measurement unit for measuring the curvature or warpage of the substrate is included.

Abstract translation: 当在加热环境中将膜沉积在半导体衬底等上时，仅仅由于温度升高，使半导体衬底在很大程度上翘曲（曲线）。 翘曲导致诸如沉积在基底上的膜的质量均匀性降低和在基底中产生裂纹的可能性高的问题。 因此，本发明的成膜装置从基板的主面的上方和下方加热基板，使得主表面的上侧和下侧之间的温度梯度（温度差）减小，并且 抑制了基板的翘曲。 更优选地包括用于测量基板的曲率或翘曲的测量单元。

公开(公告)号：US20110315998A1

公开(公告)日：2011-12-29

申请号：US13148543

申请日：2010-02-04

Applicant: Shin Hashimoto ,  Katsushi Akita ,  Shinsuke Fujiwara ,  Hideaki Nakahata ,  Kensaku Motoki

Inventor： Shin Hashimoto ,  Katsushi Akita ,  Shinsuke Fujiwara ,  Hideaki Nakahata ,  Kensaku Motoki

IPC: H01L29/20 ,  C01G15/00 ,  H01L21/20

CPC classification number: H01L21/0242 ,  C30B25/18 ,  C30B29/16 ,  C30B29/403 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/16

Abstract: A gallium nitride based semiconductor device is provided which includes a gallium nitride based semiconductor film with a flat c-plane surface provided on a gallium oxide wafer. A light emitting diode LED includes a gallium oxide support base 32 having a primary surface 32a of monoclinic gallium oxide, and a laminate structure 33 of Group III nitride. A semiconductor mesa of the laminate structure 33 includes a low-temperature GaN buffer layer 35, an n-type GaN layer 37, an active layer 39 of a quantum well structure, and a p-type gallium nitride based semiconductor layer 37. The p-type gallium nitride based semiconductor layer 37 includes, for example, a p-type AlGaN electron block layer and a p-type GaN contact layer. The primary surface 32a of the gallium oxide support base 32 is inclined at an angle of not less than 2 degrees and not more than 4 degrees relative to a (100) plane of monoclinic gallium oxide. Owing to this inclination, the gallium nitride based semiconductor epitaxially grown on the primary surface 32a of the gallium oxide support base has a flat surface.

Abstract translation: 提供了一种氮化镓基半导体器件，其包括在氧化镓晶片上设置有平坦c面的氮化镓基半导体膜。 发光二极管LED包括具有单斜氧化镓的主表面32a的氧化镓载体基底32和III族氮化物的叠层结构33。 层压结构33的半导体台面包括低温GaN缓冲层35，n型GaN层37，量子阱结构的有源层39和p型氮化镓基半导体层37. p 型氮化镓系半导体层37例如包括p型AlGaN电子阻挡层和p型GaN接触层。 氧化镓载体基体32的主表面32a相对于单斜晶系氧化镓的（100）面倾斜2度以上4度以下。 由于该倾斜，在氧化镓载体基体的主表面32a上外延生长的氮化镓基半导体具有平坦的表面。

公开(公告)号：US20110049573A1

公开(公告)日：2011-03-03

申请号：US12732775

申请日：2010-03-26

Applicant: Shin HASHIMOTO ,  Tatsuya TANABE ,  Katsushi AKITA ,  Hideaki NAKAHATA ,  Hiroshi AMANO

Inventor： Shin HASHIMOTO ,  Tatsuya TANABE ,  Katsushi AKITA ,  Hideaki NAKAHATA ,  Hiroshi AMANO

IPC: H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/2003 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/872

Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1−XN (0

Abstract translation: 提供III族氮化物半导体器件和III族氮化物半导体晶片。 III族氮化物半导体器件具有包含含有Al的III族氮化物基半导体的沟道层。 III族氮化物半导体器件可以增强二维电子气的迁移率并改善电流特性。 III族氮化物半导体晶片用于制造III族氮化物半导体器件。 III族氮化物半导体晶片包括由Al x Ga 1-x N（0

公开(公告)号：US07872285B2

公开(公告)日：2011-01-18

申请号：US11569798

申请日：2006-03-01

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

IPC: H01L29/66 ,  H01L29/207 ,  H01L29/20

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/2003 ,  H01L29/8611 ,  H01L29/872

Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm−3 or more. The donor impurity is at least either silicon or germanium.

Abstract translation: 提供具有这样的结构的垂直氮化镓半导体器件的外延衬底，其中可以在n型氮化镓衬底上提供具有期望的低载流子浓度的n型氮化镓膜。 氮化镓外延膜（65）设置在氮化镓衬底（63）上。 在氮化镓衬底（63）和氮化镓外延膜（65）中设置一个层区（67）。 氮化镓衬底（43）和氮化镓外延膜（65）之间的界面位于层区（67）中。 在层区域（67）中，供体杂质从氮化镓衬底（63）到氮化镓外延膜（65）的峰的峰值为1×1018cm-3以上。 供体杂质至少是硅或锗。

公开(公告)号：US20100230723A1

公开(公告)日：2010-09-16

申请号：US12786440

申请日：2010-05-25

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

IPC: H01L29/778 ,  H01L29/12

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462

Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25)) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.

Abstract translation: 提供具有高纯度沟道层和高电阻缓冲层的高电子迁移率晶体管。 高电子迁移率晶体管（11）设置有由氮化镓构成的支撑衬底（13），由第一氮化镓半导体构成的缓冲层（15），由第二氮化镓半导体构成的沟道层（17） 由第三氮化镓半导体构成的半导体层（19）和用于晶体管（11）的电极结构（栅电极（21），源电极（23）和漏电极（25））。 第三氮化镓半导体的带隙比第二氮化镓半导体的带隙宽。 第一氮化镓半导体的碳浓度NC1为4×1017cm-3以上。 第二氮化镓半导体的碳浓度NC2小于4×1016cm-3。

公开(公告)号：US07741207B2

公开(公告)日：2010-06-22

申请号：US11984127

申请日：2007-11-14

Applicant: Shin Hashimoto ,  Tadaaki Mimura

Inventor： Shin Hashimoto ,  Tadaaki Mimura

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/00014

Abstract: A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.

Abstract translation: 半导体器件包括形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的第一金属图案，形成在第一金属图案上的第二绝缘膜，形成在第二绝缘膜上的第二金属图案，以及第三绝缘膜 金属图案形成在第二绝缘膜中并且连接在第一金属图案和第二金属图案之间。 第三金属图案是单一连续结构，构成第三金属图案的金属的主晶体取向轴平行于半导体基板的主表面。

公开(公告)号：US20090194847A1

公开(公告)日：2009-08-06

申请号：US12096986

申请日：2006-10-16

Applicant: Shinsuke Fujiwara ,  Tomoki Uemura ,  Takuji Okahisa ,  Koji Uematsu ,  Manabu Okui ,  Muneyuki Nishioka ,  Shin Hashimoto

Inventor： Shinsuke Fujiwara ,  Tomoki Uemura ,  Takuji Okahisa ,  Koji Uematsu ,  Manabu Okui ,  Muneyuki Nishioka ,  Shin Hashimoto

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L21/02658 ,  C30B25/02 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/0254

Abstract: An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm−2 and at most 1×106 cm-31 2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.

Abstract translation: 本发明的Al x Ga y In 1-x-y N晶体基板具有面积为至少10cm 2的主平面。 主平面具有位于与主平面的外周5mm以内的外部区域和与外部区域以外的区域对应的内部区域。 内部区域的总位错密度为至少1×102cm-2，最多为1×106cm-31.2。由此，可以提供具有大尺寸和合适位错密度的Al x Ga y In 1-x-y N晶体基板，用作 用于半导体器件的衬底，包括Al x Ga y In 1-x-y N晶体衬底的半导体器件及其制造方法。

公开(公告)号：US20090051007A1

公开(公告)日：2009-02-26

申请号：US12185578

申请日：2008-08-04

Applicant: Kyoko Egashira ,  Shin Hashimoto

Inventor： Kyoko Egashira ,  Shin Hashimoto

IPC: H01L29/92

CPC classification number: H01L28/60 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.

Abstract translation: 半导体器件由以下部分构成：由第一导电膜和第二导电膜构成的互连，其从形成在基板上的绝缘膜上的互连下侧依次层叠; 以及由第一导电膜制成的下部电容电极，形成在下部电容电极上的电介质膜和形成在该电介质膜上的由上述第二导电膜构成的上部电容电极构成的电容器。