公开(公告)号：US06362066B1

公开(公告)日：2002-03-26

申请号：US09469395

申请日：1999-12-22

Applicant: Byung Ryul Ryum ,  Tae Hyeon Han ,  Soo Min Lee ,  Deok Ho Cho

Inventor： Byung Ryul Ryum ,  Tae Hyeon Han ,  Soo Min Lee ,  Deok Ho Cho

IPC: H01L21331

CPC classification number: H01L29/66287 ,  H01L29/66242

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency (fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract translation: 本发明涉及一种双极晶体管，其中使用原位掺杂的外延Si或SiGe基层代替使用离子注入的Si基，以便实现更高的截止频率。 具有比Si发射器更窄的能带隙的SiGe基极允许增强电流增益，截止频率（fT）和最大振荡频率（fmax）。 窄带隙SiGe基极还允许具有较高的基极掺杂浓度。 结果，本征基极电阻降低，噪声系数降低。 通过使用金属硅化物基极欧姆电极也使寄生基极电阻最小化。 通过简化制造工艺步骤，本发明集中在低成本，高重复性和可靠性上。

公开(公告)号：US06190984B1

公开(公告)日：2001-02-20

申请号：US09229831

申请日：1999-01-13

Applicant: Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L218222

CPC classification number: H01L29/66242

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract translation: 本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。 根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。 基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。 此外，不需要基底的选择性外延生长。 因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

公开(公告)号：US5696020A

公开(公告)日：1997-12-09

申请号：US470479

申请日：1995-06-05

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Jin-Young Kang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/76202

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.

Abstract translation: 公开了一种半导体器件的器件隔离方法，包括以下步骤：在硅衬底上顺序形成衬垫氧化膜，多晶硅膜和绝缘层，所述绝缘层由第一氧化硅膜，氮化膜 以及顺序地形成在所述多晶硅膜上的第二氧化硅膜; 通过使用图案化的光掩模来定义有源和非活性区域; 仅在非活性区域上去除绝缘层，以暴露多晶硅膜的表面; 在有源区域上的绝缘层的两个边缘处形成侧壁，所述侧壁由氮化物膜构成; 在所述多晶硅膜的表面上沉积第三氧化硅膜; 去除侧壁并将衬底蚀刻到预定深度以形成沟槽; 将绝缘材料填充到沟槽中并将其沉积到第二氧化硅上，以形成用于隔离的绝缘膜; 同时去除第二氧化硅膜和氧化硅膜，并且仅去除多晶硅膜的非活性区域; 进行热氧化以在非活性区域上形成场氧化物膜; 并依次去除形成在有源区上的隔离层和多晶硅膜。 由于在进行热氧化之前使用绝缘子填充的浅沟槽限定有源区域，所以在热氧化期间没有氧气渗透到有源区域中，由此可以形成场氧化膜而不发生鸟喙。

公开(公告)号：US5668022A

公开(公告)日：1997-09-16

申请号：US700930

申请日：1996-08-23

Applicant: Deok-Ho Cho ,  Soo-Min Lee ,  Tae-Hyeon Han ,  Byung-Ryul Ryum ,  Kwang-Eui Pyun

Inventor： Deok-Ho Cho ,  Soo-Min Lee ,  Tae-Hyeon Han ,  Byung-Ryul Ryum ,  Kwang-Eui Pyun

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  Y10S148/072

Abstract: A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.

Abstract translation: 硅/硅 - 锗双极晶体管制造方法使用金属硅化物膜作为外部基极，以降低外部基极的电阻，并且由于其自对准结构而增加最大振荡频率和截止频率。 该制造方法可以在连接到金属硅化物膜的多晶硅膜的侧壁上而不是在金属硅化物膜和下硅/硅 - 锗膜之间的界面上发生聚集，并且引导外部基极为 由绝缘体膜切割，从而实现恒定的电阻，并且还导致集成电路应用于大规模生产机构。

公开(公告)号：US08466449B2

公开(公告)日：2013-06-18

申请号：US13083990

申请日：2011-04-11

Applicant: Soo Min Lee ,  Hee Seok Park ,  Jae Woong Han ,  Seong Suk Lee ,  Cheol Soo Sone

Inventor： Soo Min Lee ,  Hee Seok Park ,  Jae Woong Han ,  Seong Suk Lee ,  Cheol Soo Sone

IPC: H01L31/00 ,  H01L33/32 ,  B82Y10/00 ,  B82Y20/00 ,  H01L33/06

CPC classification number: H01L33/32 ,  B82Y10/00 ,  B82Y20/00 ,  H01L33/06

Abstract: There is provided a nitride semiconductor device including: an n-type nitride semiconductor layer; a p-type nitride semiconductor layer; and an active layer formed between the n-type and p-type nitride semiconductor layers, the active layer including a plurality of quantum well layers and at least one quantum barrier layer deposited alternately with each other, wherein the active layer includes a first quantum well layer, a second quantum well layer formed adjacent to the first quantum well layer toward the p-type nitride semiconductor layer and having a quantum level higher than a quantum level of the first quantum well layer, and a tunneling quantum barrier layer formed between the first and second quantum well layers and having a thickness enabling a carrier to be tunneled therethrough.

Abstract translation: 提供了一种氮化物半导体器件，包括：n型氮化物半导体层; p型氮化物半导体层; 以及形成在所述n型和p型氮化物半导体层之间的有源层，所述有源层包括彼此交替沉积的多个量子阱层和至少一个量子势垒层，其中所述有源层包括第一量子阱 层，与第一量子阱层相邻形成朝向p型氮化物半导体层并且具有高于第一量子阱层的量子级的量子级的第二量子阱层，以及形成在第一量子阱层之间的隧穿量子势垒层 和第二量子阱层，并且具有能够使载体穿过其的厚度。

公开(公告)号：US20130137661A1

公开(公告)日：2013-05-30

申请号：US13511065

申请日：2010-11-19

Applicant: Seon Mi Kim ,  Min Hee Lee ,  Jae Sun Kim ,  Hoe Chul Jung ,  So Young Lee ,  Soo Min Lee ,  Eun Jeong Kim ,  Eui Sun Park ,  Sung Hoon Park ,  Bong Yong Lee ,  Key An Um

Inventor： Seon Mi Kim ,  Min Hee Lee ,  Jae Sun Kim ,  Hoe Chul Jung ,  So Young Lee ,  Soo Min Lee ,  Eun Jeong Kim ,  Eui Sun Park ,  Sung Hoon Park ,  Bong Yong Lee ,  Key An Um

IPC: C07D239/545 ,  C07D405/12 ,  C07D401/04 ,  C07D403/04 ,  C07D401/14 ,  C07D491/048 ,  C07D253/075 ,  C07D213/74 ,  C07D413/12 ,  C07D409/12 ,  C07D417/12 ,  C07D403/12 ,  C07D487/04 ,  C07D405/14 ,  C07D409/14 ,  C07F9/6558 ,  C07D403/06 ,  C07D401/12

CPC classification number: C07D239/545 ,  A61K31/506 ,  C07D213/74 ,  C07D239/46 ,  C07D253/075 ,  C07D401/04 ,  C07D401/12 ,  C07D401/14 ,  C07D403/04 ,  C07D403/06 ,  C07D403/12 ,  C07D405/12 ,  C07D405/14 ,  C07D409/12 ,  C07D409/14 ,  C07D413/12 ,  C07D417/12 ,  C07D487/04 ,  C07D491/048 ,  C07F9/65583 ,  C07F9/65586

Abstract: Disclosed are compounds useful as gonadotrophin-releasing hormone (“GnRH”) receptor antagonist.

Abstract translation: 公开了可用作促性腺激素释放激素（“GnRH”）受体拮抗剂的化合物。

公开(公告)号：US08334156B2

公开(公告)日：2012-12-18

申请号：US12648787

申请日：2009-12-29

Applicant: Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

Inventor： Cheol Kyu Kim ,  Yung Ho Ryu ,  Soo Min Lee ,  Jong In Yang ,  Tae Hyung Kim

IPC: H01L21/205

CPC classification number: H01L29/2003 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02664 ,  H01L33/0075

Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 μm. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.

Abstract translation: 氮化物半导体单晶衬底，其制造方法和使用其的垂直氮化物半导体器件的制造方法。 根据本发明的一个方面，在氮化物半导体单晶衬底中，沿着厚度方向分割上部和下部区域，所述氮化物单晶衬底的厚度至少为100μm。 这里，上部区域的掺杂浓度为下部区域的5倍以上。 优选地，上部区域中的基板的顶表面具有Ga极性。 此外，根据本发明的具体实施例，下部区域有意地未掺杂，并且上部区域是n掺杂的。 优选地，上部区域和下部区域中的每一个具有在厚度方向上基本相同的掺杂浓度。

公开(公告)号：US08274069B2

公开(公告)日：2012-09-25

申请号：US12333531

申请日：2008-12-12

Applicant: Hun Jae Chung ,  Cheol Soo Sone ,  Sung Hwan Jang ,  Rak Jun Choi ,  Soo Min Lee

Inventor： Hun Jae Chung ,  Cheol Soo Sone ,  Sung Hwan Jang ,  Rak Jun Choi ,  Soo Min Lee

IPC: H01L33/00

CPC classification number: H01L33/06 ,  H01L33/32

Abstract: There is provided a nitride semiconductor light emitting device. A nitride semiconductor light emitting device according to an aspect of the invention may include: an n-type nitride semiconductor layer provided on a substrate; an active layer provided on the n-type nitride semiconductor layer, and including quantum barrier layers and quantum well layers; and a p-type nitride semiconductor layer provided on the active layer, wherein each of the quantum barrier layers includes a plurality of InxGa(1-x)N layers (0

Abstract translation: 提供了一种氮化物半导体发光器件。 根据本发明的一个方面的氮化物半导体发光器件可以包括：设置在衬底上的n型氮化物半导体层; 设置在n型氮化物半导体层上的有源层，并且包括量子势垒层和量子阱层; 以及设置在有源层上的p型氮化物半导体层，其中每个量子势垒层包括多个In x Ga（1-x）N层（0

公开(公告)号：US20100176374A1

公开(公告)日：2010-07-15

申请号：US12352941

申请日：2009-01-13

Applicant: Jae Woong HAN ,  Hee Seok PARK ,  Seong Suk LEE ,  Soo Min LEE

Inventor： Jae Woong HAN ,  Hee Seok PARK ,  Seong Suk LEE ,  Soo Min LEE

IPC: H01L29/66

CPC classification number: H01L33/06 ,  H01L33/32

Abstract: A nitride semiconductor device according to an aspect of the invention may include: first and second conductive nitride semiconductor layers; and an active layer having a DH structure located between the first and second conductive nitride semiconductor layers, and including a single quantum well structure active layer having the single quantum well structure includes at least one polarization relaxation layer formed of a nitride single crystal having a higher energy band gap than the quantum well.

Abstract translation: 根据本发明的一个方面的氮化物半导体器件可以包括：第一和第二导电氮化物半导体层; 并且具有位于第一和第二导电氮化物半导体层之间的DH结构的有源层，并且包括具有单量子阱结构的单量子阱结构有源层包括至少一个偏振弛豫层，该偏振弛豫层由具有较高 能带隙比量子阱。

公开(公告)号：US07740823B2

公开(公告)日：2010-06-22

申请号：US11976237

申请日：2007-10-23

Applicant: Oleg Ledyaev ,  Ki Ho Park ,  Si Hyuk Lee ,  Soo Min Lee

Inventor： Oleg Ledyaev ,  Ki Ho Park ,  Si Hyuk Lee ,  Soo Min Lee

IPC: C01B21/06

CPC classification number: C30B25/18 ,  C30B29/403

Abstract: A method of growing a III group nitride single crystal by using a metal-organic chemical vapor deposition (MOCVD) process, the method including: preparing an r-plane (1-102) substrate; forming a nitride-based nucleation layer on the substrate; and growing a nonpolar a-plane nitride gallium single crystal on the nitride-based nucleation layer while altering increase and decrease of a ratio of V/III group to alternate a horizontal growth mode and a vertical growth mode.

Abstract translation: 一种通过使用金属有机化学气相沉积（MOCVD）法生长III族氮化物单晶的方法，所述方法包括：制备r-平面（1-102）衬底; 在基板上形成氮化物基成核层; 并且在氮化物基成核层上生长非极性a面平面氮化镓镓单晶，同时改变V / III基团的比例的增加和减小以交替水平生长模式和垂直生长模式。