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    DYNAMIC CACHE PREFETCHING BASED ON POWER GATING AND PREFETCHING POLICIES
    31.
    发明申请
    DYNAMIC CACHE PREFETCHING BASED ON POWER GATING AND PREFETCHING POLICIES 审中-公开
    基于功率增益和预选策略的动态缓存预测

    公开(公告)号：US20160034023A1

    公开(公告)日：2016-02-04

    申请号：US14448096

    申请日：2014-07-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Manish ARORA ,  Indrani Paul ,  Yasuko Eckert ,  Joseph L. Greathouse ,  Srilatha Manne

    IPC: G06F1/32 ,  G06F12/08

    CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/502 ,  Y02D10/14

    Abstract: A system may determine that a processor has powered up. The system may determine a first prefetching policy based on determining that the processor has powered up. The system may fetch information, from a main memory and for storage by a cache associated with the processor, using the first prefetching policy. The system may determine, after fetching information using the first prefetching policy, to apply a second prefetching policy that is different than the first prefetching policy. The system may fetch information, from the main memory and for storage by the cache, using the second prefetching policy.

    Abstract translation: 系统可以确定处理器已经通电。 该系统可以基于确定处理器通电来确定第一预取策略。 系统可以使用第一预取策略从主存储器获取信息，并且由与处理器相关联的高速缓存存储信息。 在使用第一预取策略获取信息之后，系统可以确定应用与第一预取策略不同的第二预取策略。 系统可以使用第二预取策略从主存储器获取信息并由高速缓存存储。

    POWER GATING BASED ON CACHE DIRTINESS
    32.
    发明申请
    POWER GATING BASED ON CACHE DIRTINESS 有权
    基于CACHE DIRTINESS的功率增益

    公开(公告)号：US20150185801A1

    公开(公告)日：2015-07-02

    申请号：US14146591

    申请日：2014-01-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne ,  Madhu Saravana Sibi Govindan ,  William L. Bircher

    IPC: G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3225 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

    Abstract translation: 电源选通决定可以基于缓存污垢的测量。 分析器逻辑可以基于与组件相关联的一个或多个高速缓存的高速缓存污垢来选择性地加电处理系统的组件。 当高速缓存污物超过阈值时，分析器逻辑可以对组件供电，并且当高速缓存污垢不超过阈值时，分析器逻辑可以维持组件处于空闲状态。 空闲时间预测逻辑可以用于预测组件的空闲时间的持续时间。 然后，分析器逻辑可以基于高速缓存污物和预测的空闲时间选择性地对组件进行加电。

    POWER MANAGER FOR MULTI-THREADED DATA PROCESSOR
    33.
    发明申请
    POWER MANAGER FOR MULTI-THREADED DATA PROCESSOR 审中-公开
    多线程数据处理器的电源管理器

    公开(公告)号：US20150067356A1

    公开(公告)日：2015-03-05

    申请号：US14015369

    申请日：2013-08-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vignesh Trichy Ravi ,  Manish Arora ,  William Brantley ,  Srilatha Manne ,  Indrani Paul ,  Michael Schulte

    IPC: G06F1/26

    CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

    Abstract: A data processing system includes a plurality of processor resources, a manager, and a power distributor. Each of the plurality of data processor cores is operable at a selected one of a plurality of performance states. The manager assigns each of a plurality of program elements to one of the plurality of processor resources, and synchronizing the program elements using barriers. The power distributor is coupled to the manager and to the plurality of processor resources, and assigns a performance state to each of the plurality of processor resources within an overall power budget, and in response to detecting that a program element assigned to a first processor resource is at a barrier, increases the performance state of a second processor resource that is not at the barrier within the overall power budget.

    Abstract translation: 数据处理系统包括多个处理器资源，管理器和功率分配器。 多个数据处理器核心中的每一个可操作在多个执行状态中的选定的一个。 管理器将多个程序元素中的每一个分配给多个处理器资源中的一个，并且使用屏障同步程序元素。 功率分配器耦合到管理器和多个处理器资源，并且在总功率预算内为多个处理器资源中的每一个分配一个性能状态，并且响应于检测到分配给第一处理器资源的程序元件 处于障碍之下，增加在整个功率预算范围内不处于障碍的第二处理器资源的性能状态。

    VOLTAGE REGULATOR WITH PROGRAMMABLE TELEMETRY CONFIGURATION
    34.
    发明申请
    VOLTAGE REGULATOR WITH PROGRAMMABLE TELEMETRY CONFIGURATION 有权

    公开(公告)号：US20250112639A1

    公开(公告)日：2025-04-03

    申请号：US18478892

    申请日：2023-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Wei Han ,  Meeta Surendramohan Srivastav ,  LiLi Chen ,  Indrani Paul

    IPC: H03M1/36 ,  H03M1/16 ,  H04Q9/00

    Abstract: An apparatus can include: a processor; a voltage regulator configured to provide a processor voltage and a processor current to the processor; and a voltage regulator controller that can include a current sensor comprising an analog-to-digital converter (ADC) having an ADC input range and configured to provide current data based on an ADC input voltage, and a configuration manager configured to receive processor power data and adjust the ADC input range based on the processor power data. Various other methods, systems, and computer-readable media are also disclosed.

    MEMORY SELF-REFRESH POWER GATING
    35.
    发明申请
    MEMORY SELF-REFRESH POWER GATING 有权

    公开(公告)号：US20250037750A1

    公开(公告)日：2025-01-30

    申请号：US18783900

    申请日：2024-07-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Indrani Paul ,  Benjamin Tsien ,  James R. Magro

    IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/406

    Abstract: The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.

    INPUT/OUTPUT STUTTER WAKE ALIGNMENT
    37.
    发明公开
    INPUT/OUTPUT STUTTER WAKE ALIGNMENT 审中-公开

    公开(公告)号：US20240004721A1

    公开(公告)日：2024-01-04

    申请号：US17853294

    申请日：2022-06-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Indrani Paul ,  Alexander J. Branover ,  Benjamin Tsien ,  Elliot H. Mednick

    IPC: G06F9/50

    CPC classification number: G06F9/5083 ,  G06F9/5038 ,  G06F9/5033 ,  G06F9/5016

    Abstract: An apparatus and method for efficiently performing power management for a multi-client computing system. In various implementations, a computing system includes multiple clients that process tasks corresponding to applications. The clients store generated requests of a particular type while processing tasks. A client receives an indication specifying that another client is having requests of the particular type being serviced. In response to receiving this indication, the client inserts a first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing. When the client determines a particular time interval has elapsed, the client sends an indication to other clients specifying that requests of the particular type are being serviced. The client also inserts a second urgency level different from the first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing.

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