公开(公告)号：US12211506B2

公开(公告)日：2025-01-28

申请号：US18501786

申请日：2023-11-03

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/22 ,  G06F1/32 ,  G06F1/3228 ,  G06F1/3287 ,  G06F3/16 ,  G10L13/00 ,  G10L15/00 ,  G10L15/28 ,  G10L15/08 ,  G10L25/48

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US20210341317A1

公开(公告)日：2021-11-04

申请号：US17372764

申请日：2021-07-12

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F13/16 ,  G06F1/3293 ,  G06F1/3206 ,  G06F1/3287

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US10310586B2

公开(公告)日：2019-06-04

申请号：US14980912

申请日：2015-12-28

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Shinye Shiu ,  Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Pulkit Desai ,  Rong Zhang Hu

IPC: G06F1/3218 ,  G06F1/3234 ,  G06F3/14 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395 ,  G06F1/3287 ,  G06F12/0873

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

公开(公告)号：US10261894B2

公开(公告)日：2019-04-16

申请号：US15447328

申请日：2017-03-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G06F12/02 ,  G06F12/06 ,  G06F1/32 ,  G06F3/06 ,  G06F9/44 ,  G06F13/16 ,  G06F13/40 ,  G11C11/406 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/4401 ,  G06F13/42

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US20190012484A1

公开(公告)日：2019-01-10

申请号：US15748893

申请日：2016-08-25

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F21/78 ,  G06F12/14 ,  G06F12/1027 ,  G06F12/02 ,  H04L9/08

CPC classification number: G06F21/72 ,  G06F12/0246 ,  G06F12/1027 ,  G06F12/1408 ,  G06F21/78 ,  G06F2212/7206 ,  G06F2212/7208 ,  G06F2221/2143 ,  H04L9/0861 ,  H04L9/0894 ,  H04L2209/12

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US10175905B2

公开(公告)日：2019-01-08

申请号：US15263833

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Liang Deng ,  Kai Lun Hsiung ,  Manu Gulati ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Venkata Ramana Malladi ,  Gregory S. Mathews ,  Enming Zheng ,  Fabien S. Faure

IPC: G06F1/32 ,  G06F3/06 ,  G06F1/08 ,  G06F13/16 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

公开(公告)号：US10079019B2

公开(公告)日：2018-09-18

申请号：US14109101

申请日：2013-12-17

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/22 ,  G10L15/28 ,  G06F3/16 ,  G06F1/32 ,  G10L15/08 ,  G10L25/48

CPC classification number: G10L15/28 ,  G06F1/32 ,  G06F1/3228 ,  G06F1/3287 ,  G06F3/165 ,  G10L15/22 ,  G10L25/48 ,  G10L2015/088 ,  Y02D10/171

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US10048720B2

公开(公告)日：2018-08-14

申请号：US15831732

申请日：2017-12-05

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Kiran B. Kattel ,  Manu Gulati

IPC: G06F1/12

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

公开(公告)号：US10031000B2

公开(公告)日：2018-07-24

申请号：US14458885

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G06F1/32 ,  G01D9/00 ,  G06F13/16

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US09959124B1

公开(公告)日：2018-05-01

申请号：US14498428

申请日：2014-09-26

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Manu Gulati ,  Erik P. Machnicki ,  Timothy R. Paaske

IPC: G06F1/32 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F1/3287 ,  G06F9/4411 ,  G06F9/4418

Abstract: In an embodiment, a system includes a functional unit that remains powered when the remainder of the system is powered off. The functional unit may, in response to a transition from a first power state to a second power state, retrieve configuration information from a read-only memory. In some embodiments, may be configured to store at least a portion of the configured information in a secure portion of a memory included in the functional unit and then lock the secure portion of the memory. The functional unit may then complete the transition to the second power state.