公开(公告)号：US09923081B1

公开(公告)日：2018-03-20

申请号：US15479091

申请日：2017-04-04

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Flora Fong-Song Chang ,  Abhishek Dube ,  Xuebin Li ,  Errol Antonio C. Sanchez ,  Hua Chung ,  Schubert S. Chu

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167

CPC classification number: H01L29/6659 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7851

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US09865706B2

公开(公告)日：2018-01-09

申请号：US15277394

申请日：2016-09-27

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Chun Yan

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02057 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/8252 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/78681 ,  H01L29/78696

Abstract: Embodiments described herein generally relate to methods and structures for forming precise fins comprising Group III-V elements on a silicon substrate. A buffer layer is deposited in a trench formed in the dielectric material on a substrate. An isolation layer is then deposited over the buffer layer. A portion of the isolation layer is removed allowing for a precisely sized Group III-V channel layer to be deposited on the isolation layer.

公开(公告)号：US09805914B2

公开(公告)日：2017-10-31

申请号：US14698556

申请日：2015-04-28

Applicant: APPLIED MATERIALS, INC.

Inventor： Chun Yan ,  Jim Zhongyi He ,  Xinyu Bao ,  Teng-Fang Kuo ,  Zhenwen Ding ,  Adam Lane

IPC: B08B6/00 ,  C25F1/00 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01J37/32082 ,  H01J37/32862 ,  H01L21/02057 ,  H01L21/02068 ,  H01L21/02538 ,  H01L21/02661

Abstract: Methods for removing contamination from a surface disposed in a substrate processing system are provided herein. In some embodiments, a method for removing contaminants from a surface includes: providing a first process gas comprising a chlorine containing gas, a hydrogen containing gas, and an inert gas to a process chamber having the surface disposed within the process chamber; igniting the first process gas to form a plasma from the first process gas; and exposing the surface to the plasma to remove contaminants from the surface. In some embodiments, the surface is an exposed surface of a process chamber component. In some embodiments, the surface is a surface of a first layer disposed atop a substrate, such as a semiconductor wafer.

公开(公告)号：US09653291B2

公开(公告)日：2017-05-16

申请号：US14540104

申请日：2014-11-13

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao

IPC: H01L21/306 ,  H01L21/02 ,  B08B7/00 ,  B08B7/04 ,  B08B5/00

CPC classification number: H01L21/02661 ,  B08B5/00 ,  B08B7/0035 ,  B08B7/0071 ,  B08B7/04 ,  H01L21/02046 ,  H01L21/0206 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/67115

Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius.

公开(公告)号：US09293523B2

公开(公告)日：2016-03-22

申请号：US14313086

申请日：2014-06-24

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Errol Antonio C. Sanchez

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/78 ,  H01L21/18 ,  H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L29/205 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L29/0607 ,  B82Y10/00 ,  H01L21/02546 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0673 ,  H01L29/0688 ,  H01L29/1033 ,  H01L29/12 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Embodiments of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one embodiment, a first trench is formed in a dielectric layer formed on a substrate to expose a surface of the substrate, a multi-stack layer structure is formed within the first trench, and a third semiconductor compound layer is formed on the second semiconductor compound layer, wherein the second semiconductor compound layer has an etching resistance against an etchant lower than that of the first and third semiconductor compound layers, a second trench is formed in the dielectric layer to partially expose at least the second semiconductor compound layer and the third semiconductor compound layer, and the second semiconductor compound layer is selectively removed so that the first semiconductor compound layer is isolated from the third semiconductor compound layer by an air gap.

Abstract translation: 本公开的实施例涉及半导体器件，例如用于放大或切换电子信号的晶体管。 在一个实施例中，在形成在基板上的电介质层中形成第一沟槽以暴露衬底的表面，在第一沟槽内形成多层叠层结构，在第二半导体上形成第三半导体化合物层 化合物层，其中所述第二半导体化合物层对于蚀刻剂具有比所述第一和第三半导体化合物层低的蚀刻剂的耐蚀刻性，在所述电介质层中形成第二沟槽，以至少部分地暴露所述第二半导体化合物层和所述第三半导体化合物层 半导体化合物层，并且第二半导体化合物层被选择性地去除，使得第一半导体化合物层通过气隙与第三半导体化合物层隔离。

公开(公告)号：US09159554B2

公开(公告)日：2015-10-13

申请号：US14262400

申请日：2014-04-25

Applicant: Applied Materials, Inc.

Inventor： Errol Antonio C. Sanchez ,  Xinyu Bao ,  Wonseok Lee ,  David Keith Carlson ,  Zhiyuan Ye

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02546 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/762

Abstract: Embodiments described herein generally relate to a method of fabrication of a device structure comprising Group III-V elements on a substrate. A surface may be formed on a substrate and a Group III-V material may be grown from the surface to form a Group III-V device structure in a trench isolated between a dielectric layer. A final critical dimension of the device structure may be trimmed to achieve a suitably sized node structure.

Abstract translation: 本文描述的实施例通常涉及在衬底上制造包含III-V族元素的器件结构的方法。 可以在衬底上形成A 111表面，并且可以从III族表面生长III-V族材料，以在介电层之间隔离的沟槽中形成III-V族器件结构。 可以修剪设备结构的最终关键尺寸以实现适当尺寸的节点结构。