公开(公告)号：US20140030889A1

公开(公告)日：2014-01-30

申请号：US13560688

申请日：2012-07-27

申请人： Feng Chen ,  Tsung-Han Yang ,  Juwen Gao ,  Michal Danek

发明人： Feng Chen ,  Tsung-Han Yang ,  Juwen Gao ,  Michal Danek

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  C23C16/0245 ,  C23C16/045 ,  C23C16/18 ,  C23C16/45536 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862

摘要： Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.

摘要翻译： 提供了使用具有良好填充而不使用成核层的低电阻率钨层填充特征的方法。 在某些实施方案中，该方法涉及在高分压氢存在下化学气相沉积钨之前的任选处理方法。 根据各种实施方案，处理过程可以包括均热步骤或等离子体处理步骤。 所得到的钨层由于消除常规钨成核层而降低了先进钨技术中的总接触电阻。

公开(公告)号：US06652718B1

公开(公告)日：2003-11-25

申请号：US10060724

申请日：2002-01-30

申请人： Gerard C. D'Couto ,  George Tkach ,  Michal Danek

发明人： Gerard C. D'Couto ,  George Tkach ,  Michal Danek

IPC分类号： C23C1434

CPC分类号： C23C14/345 ,  C23C14/025 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/3407 ,  H01L21/2855 ,  H01L21/28568

摘要： A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings of 6:1 is disclosed. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron apparatus in combination with an RF biased electrostatic chuck to modulate the properties of the deposited Ti and TiN layers in the same chamber, without the use of a collimator or a shutter. The resulting Ti and TiN layers are superior in step coverage, grain size, grain orientation, roughness and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.

摘要翻译： 公开了一种在通孔内沉积包括Ti和TiN的薄膜的方法，并且具有6：1的高纵横比开口的沟槽。 Ti和TiN层在中空阴极磁控管装置中使用非氮化模式的Ti靶，与RF偏置静电卡盘组合形成在集成电路基板上，以调制沉积的Ti和TiN层的性质 不使用准直器或快门。 所得到的Ti和TiN层在台阶覆盖率，晶粒尺寸，晶粒取向，粗糙度和均匀性方面都是优异的，因此随后的高纵横比开口的填充基本上无空隙。

公开(公告)号：US06541374B1

公开(公告)日：2003-04-01

申请号：US09965471

申请日：2001-09-26

申请人： Tarek Suwwan de Felipe ,  Michal Danek ,  Erich Klawuhn ,  Ronald A. Powell

发明人： Tarek Suwwan de Felipe ,  Michal Danek ,  Erich Klawuhn ,  Ronald A. Powell

IPC分类号： H01L214763

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/76813 ,  H01L21/76856

摘要： The present invention pertains to methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention allow selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and dielectric regions and conversion of the metal-nitride barrier material into an effective diffusion barrier layer having low via resistance. In a preferred method using TiN, differential morphology in a single barrier layer deposition is achieved by controlling CVD process conditions. It is believed that the absolute amount of TiN deposited on the conductor is not reduced, but the morphology of is changed so that there is little or no increase in the via resistance after barrier formation. The invention also pertains to novel integrated circuit structures resulting from application of the described methods.

摘要翻译： 本发明涉及在集成电路制造的上下文中形成扩散阻挡层的方法。 本发明的方法允许在具有暴露的导体和电介质区域的部分制造的集成电路上选择性地沉积金属氮化物阻挡层材料，并且将金属氮化物阻挡材料转化成具有低通孔电阻的有效扩散阻挡层。 在使用TiN的优选方法中，通过控制CVD工艺条件来实现单个阻挡层沉积中的微分形态。 据信，沉积在导体上的TiN的绝对量不降低，但是形态发生变化，使得阻挡层形成后的通孔电阻几乎不增加或没有增加。 本发明还涉及由应用所述方法产生的新型集成电路结构。

公开(公告)号：US06444036B2

公开(公告)日：2002-09-03

申请号：US09737681

申请日：2000-12-15

申请人： Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

发明人： Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

IPC分类号： B05C1100

CPC分类号： H01L21/76864 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4581 ,  C23C16/4586 ,  C23C16/481 ,  C23C16/5096 ,  C23C16/56 ,  H01J37/32174 ,  H01J2237/2001 ,  H01J2237/336 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862

摘要： The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber. The rf signal means is coupled to the showerhead and the wafer support for providing a first rf signal to the showerhead and a second rf signal to the wafer support.

摘要翻译： 放置在处理室中的晶片上的膜的构造可以通过以下步骤进行。 在晶片上沉积一层材料。 接下来，将材料层退火。 一旦退火完成，材料可能被氧化。 或者，一旦退火完成，材料可能暴露于硅气体。 沉积，退火和氧化或硅气体暴露都可以在相同的室中进行，而不需要从腔室中移除晶片，直到完成所有三个步骤。 用于进行这种原位结构的半导体晶片处理室可以包括处理室，喷头，晶片支架和射频信号装置。 淋浴头将气体供应到处理室中，而晶片支撑件在处理室中支撑晶片。 rf信号装置耦合到喷头和晶片支架，用于向喷头提供第一rf信号，并将第二rf信号耦合到晶片支架。

公开(公告)号：US5964947A

公开(公告)日：1999-10-12

申请号：US857847

申请日：1997-05-16

申请人： Jun Zhao ,  Ashok Sinha ,  Avi Tepman ,  Mei Chang ,  Lee Luo ,  Alex Schreiber ,  Talex Sajoto ,  Stefan Wolff ,  Charles Dornfest ,  Michal Danek

发明人： Jun Zhao ,  Ashok Sinha ,  Avi Tepman ,  Mei Chang ,  Lee Luo ,  Alex Schreiber ,  Talex Sajoto ,  Stefan Wolff ,  Charles Dornfest ,  Michal Danek

IPC分类号： C23C16/44 ,  C23C16/448 ,  C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  C23C16/509 ,  C23C16/54 ,  H01J37/32 ,  H01L21/205 ,  H01L21/285 ,  C23C16/00

CPC分类号： C23C16/45508 ,  C23C16/4411 ,  C23C16/4412 ,  C23C16/4585 ,  C23C16/46 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/3244 ,  H01J37/32477 ,  H01J37/32834 ,  H01J2237/2001

摘要： A substrate processing chamber, particularly a chemical vapor deposition (CVD) chamber used both for thermal deposition of a conductive material and a subsequently performed plasma process. The invention reduces thermal deposition of the conductive material in a pumping channel exhausting the chamber. The pumping channel is lined with various elements, some of which are electrically floating and which are designed so that conductive material deposited on these elements do not deleteriously affect a plasma generated for processing the wafer.

摘要翻译： 衬底处理室，特别是用于导电材料的热沉积和随后执行的等离子体工艺的化学气相沉积（CVD）室。 本发明减少了在排出室的泵送通道中导电材料的热沉积。 泵浦通道衬有各种元件，其中一些元件是电浮动的，并且被设计成使得沉积在这些元件上的导电材料不会有害地影响用于处理晶片的等离子体。

公开(公告)号：US07199048B2

公开(公告)日：2007-04-03

申请号：US10897479

申请日：2004-07-23

申请人： Karen Chu ,  Anil Vijayendran ,  Michal Danek

发明人： Karen Chu ,  Anil Vijayendran ,  Michal Danek

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods and structures are provided for conformal lining of dual damascene structures in semiconductor devices that contain porous or low k dielectrics. Features, such as trenches and contact vias are formed in the dielectrics. The features are subjected to low-power plasma predeposition treatment to irregularities on the porous surfaces and/or reactively form an permeation barrier before a diffusion barrier material is deposited on the feature. The diffusion barrier may, for example, be deposited by CVD using metalorganic vapor reagents. The feature is then filled with copper metal and further processed to complete a dual damascene interconnect. The plasma predeposition treatment advantageously reduces the amount of permeation of the metalorganic reagent into the interlayer dielectric.

摘要翻译： 为包含多孔或低k电介质的半导体器件中的双镶嵌结构的保形衬里提供了方法和结构。 在电介质中形成诸如沟槽和接触通孔的特征。 这些特征经受低功率等离子体预沉积处理到多孔表面上的不规则性和/或在扩散阻挡材料沉积在特征上之前反应形成渗透屏障。 可以使用金属有机蒸汽试剂通过CVD沉积扩散阻挡层。 该特征然后用铜金属填充并进一步处理以完成双镶嵌互连。 等离子体预沉积处理有利地减少了金属有机试剂渗透到层间电介质中的量。

公开(公告)号：US07037830B1

公开(公告)日：2006-05-02

申请号：US09675627

申请日：2000-09-29

申请人： Michael Rumer ,  Jack Griswold ,  Tom Dorsh ,  Michael Kwok Leung Ng ,  David E. Reedy ,  Paul D. Healey ,  Michal Danek ,  Reed W. Rosenberg

发明人： Michael Rumer ,  Jack Griswold ,  Tom Dorsh ,  Michael Kwok Leung Ng ,  David E. Reedy ,  Paul D. Healey ,  Michal Danek ,  Reed W. Rosenberg

IPC分类号： H01L21/441 ,  H01L21/445

CPC分类号： H01L21/7685 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76838 ,  H01L21/76876 ,  H01L2221/1078

摘要： A physical vapor deposition sputtering process for enhancing the preferred orientation of a titanium layer uses hydrogen before or during the deposition process. Using the oriented titanium layer as a base layer for a titanium, titanium nitride, aluminum interconnect stack results in formation of an aluminum layer with predominant crystallographic orientation which provides enhanced resistance to electromigration. In one process, a mixture of an inert gas, usually argon, and hydrogen is used as the sputtering gas for PVD deposition of titanium in place of pure argon. Alternatively, titanium is deposited in a two-step process in which an initial burst of hydrogen is introduced into the reaction chamber in a separate, first step. Pure argon is used as the sputtering gas for the titanium deposition in a second step. The method is broadly applicable to the deposition of metallization layers.

摘要翻译： 用于增强钛层的优选取向的物理气相沉积溅射方法在沉积过程之前或期间使用氢。 使用取向钛层作为钛，氮化钛，铝互连叠层的基底层导致形成具有主要<111>晶体取向的铝层，其提供增强的电迁移阻力。 在一个方法中，使用惰性气体，通常为氩气和氢气的混合物作为用于PVD沉积钛以代替纯氩气的溅射气体。 或者，钛以两步法沉积，其中在第一步骤中将初始爆发的氢气引入反应室。 在第二步中使用纯氩作为用于钛沉积的溅射气体。 该方法广泛适用于金属化层的沉积。

公开(公告)号：US06642146B1

公开(公告)日：2003-11-04

申请号：US10121949

申请日：2002-04-10

申请人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

发明人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865

摘要： The present invention pertains to methods for depositing a metal seed layer on a wafer substrate having a plurality of recessed features. Methods of the invention include at least two operations. A first portion of a seed layer is deposited such that metal ions impinge on the wafer substrate substantially perpendicular to the wafer substrate work surface. The first portion is characterized by heavy bottom coverage in the recessed features and minimal overhang on the apertures of the recessed features. A second portion of the metal seed layer is deposited with simultaneous re-sputter of at least part of the first portion that covers the bottom of the features. During re-sputter, part of the seed material on the bottom is redistributed to the sidewalls of the features. Seed layers of the invention have minimal overhang and excellent step coverage.

摘要翻译： 本发明涉及在具有多个凹陷特征的晶片衬底上沉积金属晶种层的方法。 本发明的方法包括至少两个操作。 种子层的第一部分被沉积，使得金属离子基本上垂直于晶片衬底工作表面撞击在晶片衬底上。 第一部分的特征在于凹陷特征中的重底部覆盖和凹陷特征的孔上的最小突出。 沉积金属种子层的第二部分，同时重新溅射覆盖特征底部的第一部分的至少一部分。 在重新溅射期间，底部的种子材料的一部分重新分布到特征的侧壁。 本发明的种子层具有最小的悬垂和优异的阶梯覆盖。

公开(公告)号：US06554914B1

公开(公告)日：2003-04-29

申请号：US09776704

申请日：2001-02-02

申请人： Robert T. Rozbicki ,  Ronald Allan Powell ,  Erich Klawuhn ,  Michal Danek ,  Karl B. Levy ,  Jonathan David Reid ,  Mukul Khosla ,  Eliot K. Broadbent

发明人： Robert T. Rozbicki ,  Ronald Allan Powell ,  Erich Klawuhn ,  Michal Danek ,  Karl B. Levy ,  Jonathan David Reid ,  Mukul Khosla ,  Eliot K. Broadbent

IPC分类号： C23C824

CPC分类号： C23C8/10 ,  C23C8/02 ,  C23C8/34

摘要： The present invention pertains to systems and methods for passivating the copper seed layer deposited in Damascene integrated circuit manufacturing. More specifically, the invention pertains to systems and methods for depositing the copper seed layer by physical vapor deposition, while passivating the copper during or immediately after the deposition in order to prevent excessive oxidation of the copper. The invention is applicable to dual Damascene processing.

摘要翻译： 本发明涉及用于以镶嵌集成电路制造方式钝化沉积铜晶种层的系统和方法。 更具体地，本发明涉及用于通过物理气相沉积沉积铜籽晶层的系统和方法，同时在沉积期间或之后钝化铜，以防止铜的过度氧化。 本发明适用于双镶嵌加工。

公开(公告)号：US5942799A

公开(公告)日：1999-08-24

申请号：US974451

申请日：1997-11-20

申请人： Michal Danek ,  Karl B. Levy

发明人： Michal Danek ,  Karl B. Levy

IPC分类号： H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L23/53223 ,  H01L2924/0002

摘要： Multilayer diffusion barriers are used in integrated circuits. These diffusion barriers provide high electrical conductivity to carry current efficiently with fast response time, and additionally suppress diffusion between interconnect conductors, e.g. Cu, and the semiconductor device. Moreover, the present multilayer diffusion barriers adhere well to the underlying materials as well as to Cu.In a preferred embodiment, the diffusion barriers comprise bilayers, each containing a first sublayer formed of a refractory metal, or a refractory metal nitride; and a second sublayer formed of a refractory metal nitride, a refractory metal silicon nitride, a refractory metal silicon boride, or a refractory metal oxonitride.Multilayer diffusion barriers are deposited easily by CVD in a multistation module. The present structures can be applied to sub-0.25 .mu.m logic, memory and application specific circuits with Cu as the primary conductor.

摘要翻译： 多层扩散屏障用于集成电路。 这些扩散屏障提供高电导率以有效地承载电流并具有快速响应时间，并且另外抑制互连导体之间的扩散，例如， Cu和半导体器件。 此外，本发明的多层扩散屏障很好地粘附到下面的材料以及Cu上。 在优选实施例中，扩散阻挡层包括双层，每层包含由难熔金属形成的第一子层或难熔金属氮化物; 以及由难熔金属氮化物，难熔金属氮化硅，难熔金属硅化硼或难熔金属氮氧化物形成的第二子层。 多层扩散屏障通过CVD容易地沉积在多层模块中。 本结构可以应用于以Cu为主导体的0.25μm以下的逻辑，存储器和应用专用电路。