公开(公告)号：US20050285211A1

公开(公告)日：2005-12-29

申请号：US10875482

申请日：2004-06-24

申请人： Hiroaki Niimi ,  Husam Alshareef ,  Rajesh Khamankar ,  Toan Tran

发明人： Hiroaki Niimi ,  Husam Alshareef ,  Rajesh Khamankar ,  Toan Tran

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L21/3115 ,  H01L21/0214 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

摘要： The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.

摘要翻译： 本发明提供一种具有平坦氮分布的栅极电介质及其制造方法，以及制造包含平坦氮分布的集成电路的方法。 在一个实施例中，制造栅极电介质的方法包括在衬底（310）上形成栅极电介质层（410），并对栅极电介质层（410）施加含氮等离子体工艺（510），其中含氮 等离子体工艺（510）的氦与氮的比例为3:1或更高。

公开(公告)号：US20050059260A1

公开(公告)日：2005-03-17

申请号：US10810905

申请日：2004-03-26

申请人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

发明人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

IPC分类号： H01L21/00 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.

摘要翻译： 本发明教导了在最终的源极/漏极退火之前，在轻掺杂的延伸区域之间的界面处的界面氮和与氮化硅覆盖层结合的上覆绝缘层的CMOS晶体管的形成。 P沟道轻掺杂漏极，源极和漏极区域的剂量和能量可能会增加。 所得到的晶体管显示期望的高驱动电流和低截止状态的漏电流和重叠电容。

公开(公告)号：US06342420B1

公开(公告)日：2002-01-29

申请号：US09542002

申请日：2000-04-03

申请人： Akitoshi Nishimura ,  Yasutoshi Okuno ,  Rajesh Khamankar ,  Shane R. Palmer

发明人： Akitoshi Nishimura ,  Yasutoshi Okuno ,  Rajesh Khamankar ,  Shane R. Palmer

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10805 ,  Y10S257/905

摘要： An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.

摘要翻译： 用于制造六边形对称单元（例如，动态随机存取存储单元（100））的装置和方法。 电池可以包括位线触点（38），六边形围绕位线触点（38）的存储节点触点（32），也围绕位线触点（38）的存储节点（36），其中一部分形成字段 效应晶体管栅极。 位线触点（38）和存储节点触点（32）之间的大距离在光刻期间引起很大的问题，因为使用Levenson Phaseshift时很难实现暗区。 因为Levenson Phaseshift取决于附近特征之间的波浪消除，通常被称为破坏性干扰，所以模式的最终可印刷性主要是对称性和分离距离的函数。 当图案中的非对称性发生时，结果是在打印步骤期间，场的更弱的取消（即，特征之间）和图像对比度的大的损失和焦点的深度。 最终结果是通过本文公开的几何修改可以显着地减少增加设备故障的缺陷。

公开(公告)号：US6166408A

公开(公告)日：2000-12-26

申请号：US216251

申请日：1998-12-18

申请人： Akitoshi Nishimura ,  Yasutoshi Okuno ,  Rajesh Khamankar ,  Shane R. Palmer

发明人： Akitoshi Nishimura ,  Yasutoshi Okuno ,  Rajesh Khamankar ,  Shane R. Palmer

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10888 ,  H01L27/10805 ,  Y10S257/905

摘要： An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contacts (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.

摘要翻译： 用于制造六边形对称单元（例如，动态随机存取存储单元（100））的装置和方法。 电池可以包括位线触点（38），六边形围绕位线触点（38）的存储节点触点（32），也围绕位线触点（38）的存储节点（36），其中一部分形成字段 效应晶体管栅极。 位线触点（38）和存储节点触点（32）之间的大距离在光刻期间引起很大的问题，因为当使用Levenson Phaseshift时，很难实现暗区。 因为Levenson Phaseshift取决于附近特征之间的波浪消除，通常被称为破坏性干扰，所以模式的最终可印刷性主要是对称性和分离距离的函数。 当图案中的非对称性发生时，结果是在打印步骤期间，场的更弱的取消（即，特征之间）和图像对比度的大的损失和焦点的深度。 最终结果是通过本文公开的几何修改可以显着地减少增加设备故障的缺陷。

公开(公告)号：US6153490A

公开(公告)日：2000-11-28

申请号：US105738

申请日：1998-06-26

申请人： Guoqiang Xing ,  Scott R. Summerfelt ,  Rajesh Khamankar

发明人： Guoqiang Xing ,  Scott R. Summerfelt ,  Rajesh Khamankar

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/20 ,  H01L21/00 ,  H01L21/302 ,  H01L21/44

CPC分类号： H01L27/10852 ,  H01L21/32136 ,  H01L21/32139 ,  H01L28/60 ,  H01L28/55

摘要： A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer 824 between the platinum layer and the second material; forming a hardmask layer 829 over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer 832, the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti--Al--N including at least 1% of aluminum.

公开(公告)号：US08114784B2

公开(公告)日：2012-02-14

申请号：US12904593

申请日：2010-10-14

申请人： Haowen Bu ,  Che-Jen Hu ,  Rajesh Khamankar

发明人： Haowen Bu ,  Che-Jen Hu ,  Rajesh Khamankar

IPC分类号： H01L21/31

CPC分类号： H01L21/3185 ,  C23C14/0652 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7843

摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

摘要翻译： 集成电路（IC）通常含有具有压应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。 该增加受到PMD衬套的厚度的限制。 本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。 将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。 本发明的PMD衬垫由3〜10层构成。 可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。 还要求一种包含本发明的PMD衬垫的IC及其形成方法。

公开(公告)号：US08084312B2

公开(公告)日：2011-12-27

申请号：US12688442

申请日：2010-01-15

申请人： Srinivasan Chakravarthi ,  P R Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

发明人： Srinivasan Chakravarthi ,  P R Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。

公开(公告)号：US20110027953A1

公开(公告)日：2011-02-03

申请号：US12904593

申请日：2010-10-14

申请人： Haowen Bu ,  Jerry Che-Jen Hu ,  Rajesh Khamankar

发明人： Haowen Bu ,  Jerry Che-Jen Hu ,  Rajesh Khamankar

IPC分类号： H01L21/8238

CPC分类号： H01L21/3185 ,  C23C14/0652 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7843

摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

摘要翻译： 集成电路（IC）通常包含具有压缩应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。 该增加受到PMD衬套的厚度的限制。 本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。 将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。 本发明的PMD衬垫由3〜10层构成。 可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。 还要求一种包含本发明的PMD衬垫的IC及其形成方法。

公开(公告)号：US07847401B2

公开(公告)日：2010-12-07

申请号：US12437004

申请日：2009-05-07

申请人： P R Chidambaram ,  Haowen Bu ,  Rajesh Khamankar ,  Douglas T Grider

发明人： P R Chidambaram ,  Haowen Bu ,  Rajesh Khamankar ,  Douglas T Grider

IPC分类号： H01L21/00

CPC分类号： H01L21/324 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/7833

摘要： A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embodiments, including but not limited to, the formation of recess, strained device regions (224).

摘要翻译： 形成包括高温处理步骤（步骤118）的半导体结构（202）的方法（100）包括在装置（202）的受保护区域（214）上使用高温氮氧化物掩模（220） 。 本发明应用于许多不同的实施例，包括但不限于形成凹陷，应变器件区域（224）。

公开(公告)号：US20070210421A1

公开(公告)日：2007-09-13

申请号：US11374635

申请日：2006-03-13

申请人： Haowen Bu ,  Anand Krishnan ,  Ting Tsui ,  William Dostalik ,  Rajesh Khamankar

发明人： Haowen Bu ,  Anand Krishnan ,  Ting Tsui ,  William Dostalik ,  Rajesh Khamankar

IPC分类号： H01L23/58 ,  H01L21/469

CPC分类号： H01L21/02167 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides, one aspect, a method of fabricating a semiconductor device. In one aspect, the method includes forming a carbide layer over a gate electrode and depositing a pre-metal dielectric layer over the carbide layer. The method provides a significant reduction in NBTI drift.

摘要翻译： 本发明一方面提供一种制造半导体器件的方法。 一方面，该方法包括在栅电极上形成碳化物层，并在碳化物层上沉积预金属电介质层。 该方法显着降低了NBTI漂移。