公开(公告)号：US20180032281A1

公开(公告)日：2018-02-01

申请号：US15225343

申请日：2016-08-01

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Peter F. Holland ,  Erik P. Machnicki ,  Robert E. Jeter ,  Rakesh L. Notani ,  Neeraj Parik ,  Marc A. Schaub

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

公开(公告)号：US09698797B1

公开(公告)日：2017-07-04

申请号：US15210852

申请日：2016-07-14

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Suhas Kumar Suvarna Ramesh ,  Venkata Ramana Malladi ,  Thomas H. Huang ,  Rakesh L. Notani ,  Robert E. Jeter ,  Kai Lun Hsiung

IPC: H03L7/00 ,  H03L7/07 ,  H03L7/099

CPC classification number: H03L7/23

Abstract: Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).

公开(公告)号：US09666264B1

公开(公告)日：2017-05-30

申请号：US15187886

申请日：2016-06-21

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Xingchao C. Yuan

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G06F13/4234 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A method and apparatus for memory calibration averaging is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller. The memory controller includes a calibration control circuit that periodically performs calibrations of the memory subsystem. Calibration may be performed for a delay applied to a data strobe used to synchronized transfers of data between the memory controller and the memory, and a reference voltage used to distinguish between a logic 0 and a logic 1 during memory reads. Following the performance of a calibration, the values of the delay and the reference voltage may be set based on an average of a most recent number of calibrations.

公开(公告)号：US09640244B1

公开(公告)日：2017-05-02

申请号：US15083786

申请日：2016-03-29

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani

IPC: G11C29/04 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1694 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/021 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/50004 ,  G11C29/50008 ,  G11C29/50012 ,  G11C2029/1208 ,  G11C2029/5002 ,  G11C2207/2254

Abstract: A method and apparatus for pre-calibration of various system performance states is disclosed. In one embodiment, a method includes, for each of a number of different performance states (or operating points), performing initial calibrations of various parameters associated with transfers of data between a memory and a memory controller. After completing the initial calibrations, the calibrated values are stored. Thereafter, during normal operation and following a change to a new performance state, the values of the various parameters are set to the values to which they were calibrated during the initial calibration for that state.

公开(公告)号：US09209961B1

公开(公告)日：2015-12-08

申请号：US14499985

申请日：2014-09-29

Applicant: Apple Inc.

Inventor： Rakesh L. Notani

IPC: H04L7/00 ,  H03L7/08 ,  H03K5/14

CPC classification number: H04L7/0041 ,  H03K5/133 ,  H03K5/14 ,  H03K2005/00234

Abstract: A method and apparatus for delay compensation in data transmission is disclosed. In one embodiment, an IC is configured to transmit data along with a clock signal to which the data is synchronized at the receiver. The IC includes a delay circuit configured to receive the data, which is transmitted in beats. The delay circuit includes a number of pipelines corresponding to the number of beats. Beats of data input into the delay circuit are routed to particular ones of the pipelines in accordance with a desired amount of delay. The delay applied to the data may be set to align the data with the clock signal at the receiver and to compensate for inherent delays that affect the clock signal.

Abstract translation: 公开了一种用于数据传输中延迟补偿的方法和装置。 在一个实施例中，IC被配置为在接收器处与数据同步的时钟信号一起发送数据。 IC包括被配置为接收以节拍传送的数据的延迟电路。 延迟电路包括对应于节拍次数的多个管线。 根据期望的延迟量将输入到延迟电路的数据的路数路由到管道中的特定管道。 可以将施加到数据的延迟设置为使数据与接收器处的时钟信号对准，并且补偿影响时钟信号的固有延迟。

公开(公告)号：US11875871B2

公开(公告)日：2024-01-16

申请号：US18054056

申请日：2022-11-09

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

CPC classification number: G11C5/148 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G11C5/141 ,  G11C2207/2254

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

公开(公告)号：US20230115215A1

公开(公告)日：2023-04-13

申请号：US18054056

申请日：2022-11-09

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

公开(公告)号：US11527269B2

公开(公告)日：2022-12-13

申请号：US16716616

申请日：2019-12-17

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

公开(公告)号：US11226752B2

公开(公告)日：2022-01-18

申请号：US16293398

申请日：2019-03-05

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Robert E. Jeter ,  Suhas Kumar Suvarna Ramesh ,  Naveen Kumar Korada ,  Mohammad Rizwan ,  Alma L. Juarez Dominguez ,  John H. Kelm ,  Matthew R. Johnson

IPC: G06F3/06 ,  G11C7/22 ,  G11C11/4063 ,  G11C7/10

Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

公开(公告)号：US20190385670A1

公开(公告)日：2019-12-19

申请号：US16012427

申请日：2018-06-19

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Lakshmi Narasimha Murthy Nukala ,  Kai Lun Hsiung ,  Sukalpa Biswas ,  Yanzhe Liu

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074 ,  G06F13/16

Abstract: A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.