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公开(公告)号：US06962826B2
公开(公告)日：2005-11-08
申请号：US10900771
申请日：2004-07-27
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
摘要翻译： 每个包括集成电路（IC）裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附着站的探针进行电测试。 在通过将集成电路（IC）芯片压在基板上的互连点以进行电连接的环氧树脂固化之前，可以测试使用“湿”快速固化环氧树脂进行芯片附接的那些组件，而使用“干”环氧树脂的那些组件 在测试之前进行治愈。 在任一种情况下，骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定，并且消除了在维修期间使用已知好模具（KGD）返工程序的需要。
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公开(公告)号：US06954081B2
公开(公告)日：2005-10-11
申请号：US10338530
申请日：2003-01-08
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
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公开(公告)号：US06953700B2
公开(公告)日：2005-10-11
申请号：US10927546
申请日：2004-08-25
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
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公开(公告)号：US06949943B2
公开(公告)日：2005-09-27
申请号：US10900609
申请日：2004-07-27
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
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公开(公告)号：US06798057B2
公开(公告)日：2004-09-28
申请号：US10288180
申请日：2002-11-05
申请人： Todd O. Bolkin , Chad A. Cobbley
发明人： Todd O. Bolkin , Chad A. Cobbley
IPC分类号： H01L2302
CPC分类号： H01L25/105 , H01L23/3128 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/01004 , H01L2924/01012 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/1433 , H01L2924/15321 , H01L2924/15331 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A thin-stacked ball grid array (BGA) package is created by coupling a semi-conducting die to each of the opposing faces of an interposer having bond pads and circuitry on both faces. Solder balls on either side of each die and/or the interposer provide interconnects for stacking packages and also provide interconnects for module mounting. Each die may be electrically coupled to the interposer using wire bonds, “flip-chip” techniques, or other techniques as appropriate. A redistribution layer may also be formed on the outer surface of a bumped die to create connections between the die circuitry, ball pads and/or wire bonding pads. Because the two die are coupled to each other on opposite faces of the interposer, each package is extremely space-efficient. Individual packages may be stacked together prior to encapsulation or molding to further improve the stability and manufacturability of the stacked package.
摘要翻译： 通过将半导体管芯耦合到具有在两个表面上的接合焊盘和电路的插入件的每个相对面而产生薄堆叠球栅阵列（BGA）封装。 每个管芯和/或插入件两侧的焊球提供用于堆叠封装的互连，并且还提供用于模块安装的互连。 可以使用引线键合“倒装芯片”技术或适当的其它技术将每个管芯电耦合到插入器。 还可以在凸起的裸片的外表面上形成再分配层，以在管芯电路，焊盘和/或引线接合焊盘之间形成连接。 因为两个管芯在插入器的相对面上彼此耦合，所以每个封装都非常节省空间。 单个包装可以在封装或模制之前堆叠在一起，以进一步提高堆叠包装的稳定性和可制造性。
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36.发明授权公开(公告)号：US06709896B1
公开(公告)日：2004-03-23
申请号：US09651217
申请日：2000-08-30
申请人： Chad A. Cobbley , Tongbi Jiang , Edward A. Schrock
发明人： Chad A. Cobbley , Tongbi Jiang , Edward A. Schrock
IPC分类号： H01L2144
CPC分类号： H01L24/83 , H01L24/27 , H01L24/29 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2224/83194 , H01L2224/83855 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01082 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/3512
摘要： An adhesive composition and methods incorporating the adhesive composition in semiconductor applications are provided. The adhesive composition is an instant setting adhesive composition that does not require external energy input such as heat or radiation such for application of the adhesive composition on a surface. The instant setting composition possesses sufficient thixotropic characteristics such that applying the instant setting adhesive composition to a surface can be accomplished by a variety of application techniques and in a variety of patterns. Once applied to the surface, the instant setting adhesive composition sets to retain the discrete pattern as applied, in a relatively short period of time, typically from about 0.10 to about 120 seconds at an ambient temperature, typically from 20° C. to 30° C. Advantageously, the instant setting adhesive composition can be screen printed on a semiconductor wafer prior to singulation because streets between the dice are essentially free of the instant setting adhesive composition.
摘要翻译： 提供在半导体应用中粘合组合物的粘合剂组合物和方法。 粘合剂组合物是瞬间固化粘合剂组合物，其不需要诸如热或辐射的外部能量输入，以便将粘合剂组合物施加在表面上。 本发明的凝固组合物具有足够的触变特性，使得将即刻固化粘合剂组合物施加到表面可以通过各种应用技术和各种图案来实现。 一旦施加到表面上，即刻固化粘合剂组合物在相对较短的时间段内保持离散的图案，通常在约0.10至约120秒的环境温度，通常为20℃至30℃ 有利地，即刻固化粘合剂组合物可以在切割之前丝网印刷在半导体晶片上，因为骰子之间的街道基本上不含瞬时固化粘合剂组合物。
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公开(公告)号：US06607599B1
公开(公告)日：2003-08-19
申请号：US09514916
申请日：2000-02-28
申请人： Tongbi Jiang , Chad A. Cobbley , John VanNortwick
发明人： Tongbi Jiang , Chad A. Cobbley , John VanNortwick
IPC分类号： B05C1111
CPC分类号： B41C1/14 , B41N1/242 , H01L2224/4826 , H05K3/1225 , Y10S438/945
摘要： A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.
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公开(公告)号：US06558600B1
公开(公告)日：2003-05-06
申请号：US09565638
申请日：2000-05-04
IPC分类号： B29C4502
CPC分类号： B29C70/70 , B29C45/02 , B29C45/14655 , B29C45/462 , B29K2063/00 , B29K2101/10 , Y10T428/13
摘要： A method and apparatus for encapsulating a microelectronic substrate. In one embodiment, the apparatus can include a mold having an internal volume with a first portion configured to receive the microelectronic substrate coupled to a second portion configured to receive a pellet for encapsulating the microelectronic substrate. A plunger moves axially in the second portion to force the pellet into the first portion and around the microelectronic substrate. The pellet has overall external dimensions approximately the same as a conventional pellet, but has cavities or other features that reduce the volume of the pellet and the amount of pellet waste material left after the pellet encapsulates the microelectronic substrate. Accordingly, the pellet can be used with existing pellet handling machines. The mold and/or the plunger can have protrusions and/or other shape features that reduce the size of the first portion of the internal volume. In one aspect of this embodiment, the protrusions can be shaped to fit within the cavities of the pellet.
摘要翻译： 一种用于封装微电子衬底的方法和装置。 在一个实施例中，该装置可以包括具有内部体积的模具，第一部分被配置为接收耦合到第二部分的微电子衬底，该第二部分被配置为接收用于封装微电子衬底的颗粒。 柱塞在第二部分中轴向移动以迫使颗粒进入第一部分并且围绕微电子衬底。 颗粒具有与常规颗粒大致相同的整体外部尺寸，但是具有减小颗粒体积的空腔或其它特征以及颗粒封装微电子衬底之后留下的颗粒废料的量。 因此，颗粒可以与现有的颗粒处理机一起使用。 模具和/或柱塞可以具有减小内部体积的第一部分的尺寸的突起和/或其它形状特征。 在该实施例的一个方面中，突起可以成形为适合于颗粒的空腔内。
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公开(公告)号：US06545498B2
公开(公告)日：2003-04-08
申请号：US09819472
申请日：2001-03-28
IPC分类号： G01R3126
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
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公开(公告)号：US06518654B1
公开(公告)日：2003-02-11
申请号：US09834415
申请日：2001-04-13
IPC分类号： H01L2302
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/30107 , H05K3/303 , H05K3/305 , H05K3/3436 , H05K2201/10568 , H05K2201/10734 , H05K2201/10977 , H05K2201/2036 , Y02P70/613 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.
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