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公开(公告)号：US20080266689A1
公开(公告)日：2008-10-30
申请号：US11789947
申请日：2007-04-26
CPC分类号： G02B5/286 , Y10T428/259
摘要： A non-stoichiometric SiOXNY thin-film optical filter is provided. The filter is formed from a substrate and a first non-stoichiometric SiOX1NY1 thin-film overlying the substrate, where (X1+Y1 0). The first non-stoichiometric SiOX1NY1 thin-film has a refractive index (n1) in the range of about 1.46 to 3, and complex refractive index (N1=n1+ik1), where k1 is an extinction coefficient in a range of about 0 to 0.5. The first non-stoichiometric SiOX1NY1 thin-film may be either intrinsic or doped. In one aspect, the first non-stoichiometric SiOX1NY1 thin-film has nanoparticles with a size in the range of about 1 to 10 nm. A second non-stoichiometric SiOX2NY2 thin-film may overlie the first non-stoichiometric SiOX1NY1 thin-film, where Y1≠Y2. The second non-stoichiometric SiOX1NY1 thin-film may be intrinsic and doped. In another variation, a stoichiometric SiOX2NY2 thin-film, intrinsic or doped, overlies the first non-stoichiometric SiOX1NY1 thin-film.
摘要翻译： 提供非化学计量的SiO x N Y Y薄膜滤光器。 过滤器由衬底和覆盖在衬底上的第一非化学计量的SiO x N x N 1 N 1薄膜形成，其中（X1 + Y1 <2和Y1> 0） 。 第一非化学计量的SiO x N 1 N 1薄膜的折射率（n1）在约1.46至3的范围内，并且复数折射率（N1 = n1 + ik1），其中k1是约0至0.5范围内的消光系数。 第一非化学计量的SiO x N 1 N 1 X 1薄膜可以是固有的或掺杂的。 在一个方面，第一非化学计量的SiO x N 1 N 1薄膜具有尺寸在约1nm至10nm范围内的纳米颗粒。 第二非化学计量的SiO 2 X 2 N 2 O 2薄膜可以覆盖在第一非化学计量的SiO x N 1 N SUB 2 / >薄膜，其中Y1 <> Y2。 第二非化学计量的SiO x N 1 N 1 Y 1薄膜可以是固有的和掺杂的。 在另一个实施方式中，本征或掺杂的化学计量的SiO 2 X 2 N 2 O 2薄膜覆盖在第一非化学计量的SiO x N N > Y1 薄膜。
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公开(公告)号：US07186663B2
公开(公告)日：2007-03-06
申请号：US10871939
申请日：2004-06-17
IPC分类号： H01L21/31
CPC分类号： C23C16/24 , C23C16/45523 , C23C16/509 , H01L21/02422 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/049 , H01L21/31612
摘要： A method is provided for forming a Si and Si—Ge thin films. The method comprises: providing a low temperature substrate material of plastic or glass; supplying an atmosphere; performing a high-density (HD) plasma process, such as an HD PECVD process using an inductively coupled plasma (ICP) source; maintaining a substrate temperature of 400 degrees C., or less; and, forming a semiconductor layer overlying the substrate that is made from Si or Si-germanium. The HD PECVD process is capable of depositing Si at a rate of greater than 100 Å per minute. The substrate temperature can be as low as 50 degrees C. Microcrystalline Si, a-Si, or a polycrystalline Si layer can be formed over the substrate. Further, the deposited Si can be either intrinsic or doped. Typically, the supplied atmosphere includes Si and H. For example, an atmosphere can be supplied including SiH4 and H2, or comprising H2 and Silane with H2/Silane ratio in the range of 0–100.
摘要翻译： 提供了形成Si和Si-Ge薄膜的方法。 该方法包括：提供塑料或玻璃的低温基材; 提供气氛; 执行高密度（HD）等离子体处理，例如使用电感耦合等离子体（ICP）源的HD PECVD工艺; 保持基板温度在400摄氏度以下; 并且形成由Si或Si-锗制成的衬底上的半导体层。 HD PECVD工艺能够以每分钟大于100埃的速率沉积Si。 衬底温度可以低至50摄氏度。可以在衬底上形成微晶Si，a-Si或多晶Si层。 此外，沉积的Si可以是固有的或掺杂的。 通常，供给的气氛包括Si和H.例如，可以提供包括SiH 4和H 2的气体，或者包含H 2和硅烷，H 2 /硅烷比在0-100范围内。
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公开(公告)号：US06642092B1
公开(公告)日：2003-11-04
申请号：US10194895
申请日：2002-07-11
IPC分类号： H01L2100
CPC分类号： H01L27/1262 , G11C13/0007 , G11C2213/31 , H01L27/1214 , H01L27/1218 , H01L27/3244 , H01L27/3262 , H01L29/4908 , H01L29/66757 , H01L29/78603 , H01L51/0097 , H01L2251/5315 , H01L2251/5338 , Y02E10/549 , Y02P70/521
摘要： A method for is provided forming a thin-film transistor (TFT) on a flexible substrate. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, stainless steel, or Kovar, having a thickness in the range of 10 to 500 microns; depositing and annealing amorphous silicon to form polycrystalline silicon; and, thermally growing a gate insulation film overlying the polycrystalline. The silicon annealing process can be conducted at a temperature greater than 700 degrees C. using a solid-phase crystallization (SPC) annealing process. Thermally growing a gate insulation film includes: forming a polycrystalline silicon layer having a thickness in the range of 10 to 100 nanometers (nm); and, thermally oxidizing the film at temperature in the range of 900 to 1150 degrees for a period of time in the range of 2 to 60 minutes. Alternately, a plasma oxide layer is deposited over a thinner thermally oxidized layer.
摘要翻译： 提供一种在柔性基板上形成薄膜晶体管（TFT）的方法。 该方法包括：提供具有10至500微米厚度的金属箔基底如钛（Ti），铬镍铁合金，不锈钢或科瓦尔; 沉积和退火非晶硅以形成多晶硅; 并且热堆积覆盖多晶的栅极绝缘膜。 硅退火工艺可以使用固相结晶（SPC）退火工艺在大于700℃的温度下进行。 制造栅极绝缘膜的方法包括：形成厚度为10〜100纳米（nm）的多晶硅层; 并将膜的温度在900〜1150度的范围内热氧化2〜60分钟的时间。 或者，等离子体氧化物层沉积在较薄的热氧化层上。
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公开(公告)号：US08106473B2
公开(公告)日：2012-01-31
申请号：US13050689
申请日：2011-03-17
申请人： Jong-Jan Lee , Steven R. Droes , John W. Hartzell , Jer-Shen Maa
发明人： Jong-Jan Lee , Steven R. Droes , John W. Hartzell , Jer-Shen Maa
IPC分类号： H01L27/146 , H01L31/068
CPC分类号： H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14689 , H01L27/1469 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/351 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes.
摘要翻译： 玻璃基板上的锗（Ge）光电二极管阵列具有相应的制造方法。 提供未掺杂或轻掺杂第一掺杂剂的Ge衬底。 第一掺杂剂可以是n型或p型掺杂剂。 Ge衬底的第一表面适度地掺杂有第一掺杂剂并且结合到玻璃衬底顶表面。 然后，Ge衬底第二表面的第一区域被第一掺杂剂重掺杂。 Ge衬底第二表面的第二区域重掺杂有与第一掺杂剂相反的电子亲和力的第二掺杂剂，形成pn结。 在Ge衬底第二表面上形成层间电介质（ILD）层，并且在覆盖Ge衬底第二表面的第一和第二区域的ILD层中蚀刻接触孔。 接触孔填充有金属，并且金属垫形成在接触孔上。
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公开(公告)号：US20110163404A1
公开(公告)日：2011-07-07
申请号：US13050689
申请日：2011-03-17
申请人： Jong-Jan Lee , Steven R. Droes , John W. Hartzell , Jer-Shen Maa
发明人： Jong-Jan Lee , Steven R. Droes , John W. Hartzell , Jer-Shen Maa
IPC分类号： H01L27/146 , H01L31/068
CPC分类号： H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14689 , H01L27/1469 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/351 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes.
摘要翻译： 玻璃基板上的锗（Ge）光电二极管阵列具有相应的制造方法。 提供未掺杂或轻掺杂第一掺杂剂的Ge衬底。 第一掺杂剂可以是n型或p型掺杂剂。 Ge衬底的第一表面适度地掺杂有第一掺杂剂并且结合到玻璃衬底顶表面。 然后，Ge衬底第二表面的第一区域被第一掺杂剂重掺杂。 Ge衬底第二表面的第二区域重掺杂有与第一掺杂剂相反的电子亲和力的第二掺杂剂，形成pn结。 在Ge衬底第二表面上形成层间电介质（ILD）层，并且在覆盖Ge衬底第二表面的第一和第二区域的ILD层中蚀刻接触孔。 接触孔填充有金属，并且金属垫形成在接触孔上。
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公开(公告)号：US07714354B2
公开(公告)日：2010-05-11
申请号：US11978909
申请日：2007-10-30
申请人： David R. Evans , John W. Hartzell
发明人： David R. Evans , John W. Hartzell
IPC分类号： H01L29/80
CPC分类号： H01L21/288 , C23C18/1605 , C23C18/165 , C23C18/1657 , C25D1/003 , C25D5/022 , C25D5/50 , H01L21/2885 , H01L21/76885
摘要： A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).
摘要翻译： 提供了一种电铸金属集成电路结构的方法。 该方法包括：通过层间绝缘体形成诸如通孔或线的开口，暴露衬底表面; 形成覆盖层间绝缘体和衬底表面的基层; 形成覆盖基层的冲击层; 形成覆盖所述冲击层的顶层; 选择性蚀刻以去除覆盖在衬底表面上的顶层，暴露出一层击打层表面; 并且电铸在覆盖着撞击层表面的金属结构。 使用电镀或无电沉积工艺沉积电铸金属结构。 通常，金属是Cu，Au，Ir，Ru，Rh，Pd，Os，Pt或Ag。 可以使用物理气相沉积（PVD），蒸发，反应溅射或金属有机化学气相沉积（MOCVD）来沉积基底，打击和顶层。
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公开(公告)号：US20080009084A1
公开(公告)日：2008-01-10
申请号：US11524607
申请日：2006-09-21
申请人： John W. Hartzell
发明人： John W. Hartzell
IPC分类号： H01L21/00
CPC分类号： G03F7/70291 , B23K26/0613 , B23K26/3576 , B23K26/3584 , B23K26/389 , H01L21/02532 , H01L21/02678
摘要： A system and method are provided for processing a semiconductor film using a digital light valve. The method enables pixel elements from an array of selectable pixel elements; gates a light in response to enabling the pixel elements; exposes selected areas of a semiconductor film, such as Si, to the gated light; and, creates light-related reactions in the semiconductor film, in response to the light exposure. More specifically, enabling pixel elements from an array of selectable pixel elements may include: exposing a digital light valve array of selectable pixel elements to the light; enabling a pattern of pixel elements; and, transmitting light from the pattern of enabled pixel elements. Examples of light-related reactions include changing the topology of a film surface, creating a chemical reaction, diffusing a dopant, activating a dopant, alloying the semiconductor film, and changing the semiconductor crystalline structure.
摘要翻译： 提供一种用于使用数字光阀处理半导体膜的系统和方法。 该方法使得可选择像素元件的阵列中的像素元件; 响应于使像素元件能够点亮光; 将诸如Si的半导体膜的选定区域暴露于门控光; 并且响应于曝光而在半导体膜中产生光相关的反应。 更具体地，使得可选择像素元件阵列中的像素元件可以包括：将可选择像素元件的数字光阀阵列暴露于光; 实现像素元素的图案; 并且从启用像素元件的图案透射光。 光相关反应的实例包括改变膜表面的拓扑结构，产生化学反应，扩散掺杂剂，激活掺杂剂，合金化半导体膜以及改变半导体晶体结构。
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公开(公告)号：US07217588B2
公开(公告)日：2007-05-15
申请号：US11178148
申请日：2005-07-08
IPC分类号： H01L21/00
CPC分类号： B81C1/0023 , H01L27/1214
摘要： An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.
摘要翻译： 提供集成MEMS封装和相关封装方法。 该方法包括：形成电连接到第一基板的电路; 将MEMS器件集成在电连接到第一衬底的第一衬底区域上; 提供覆盖所述第一基板的第二基板; 以及沿所述第一区域边界在所述第一和第二基板之间形成壁。 在一个方面，使用薄膜工艺形成电路; 并且其中将MEMS器件集成在第一衬底区域上包括使用薄膜工艺形成MEMS，同时形成电子器件。 或者，MEMS器件以独立的工艺形成，附接到第一衬底，并且使用薄膜工艺将电互连形成到第一衬底。
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39.发明授权公开(公告)号：US06913649B2
公开(公告)日：2005-07-05
申请号：US10602186
申请日：2003-06-23
摘要： Single-crystal devices and a method for forming semiconductor film single-crystal domains are provided. The method comprises: forming a substrate, such as glass or Si; forming an insulator film overlying the substrate; forming a single-crystal seed overlying the substrate and insulator; forming an amorphous film overlying the seed; annealing the amorphous film; and, forming a single-crystal domain in the film responsive to the single-crystal seed. The annealing technique can be (conventional) laser annealing, a laser induced lateral growth (LiLAC) process, or conventional furnace annealing. In some aspects forming a single-crystal seed includes forming a nanowire or a self assembled monolayer (SAM). For example, a Si nanowire can be formed having a crystallographic orientation of or . When, the seed has a crystallographic orientation, then an n-type TFT can be formed. Likewise, when a single-crystal seed has a crystallographic orientation, a p-type TFT can be formed.
摘要翻译： 提供单晶器件和形成半导体膜单晶畴的方法。 该方法包括：形成诸如玻璃或Si的衬底; 形成覆盖在基板上的绝缘膜; 形成覆盖衬底和绝缘体的单晶种子; 形成覆盖种子的无定形膜; 退火非晶膜; 并且响应于单晶种子在膜中形成单晶畴。 退火技术可以是（常规）激光退火，激光诱导横向生长（LiLAC）工艺或常规炉退火。 在形成单晶种子的一些方面，包括形成纳米线或自组装单层（SAM）。 例如，可以形成具有<110>或<100>的晶体取向的Si纳米线。 当种子具有<100>晶体取向时，则可以形成n型TFT。 同样，当单晶种子具有<110>结晶取向时，可以形成p型TFT。
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公开(公告)号：US06902960B2
公开(公告)日：2005-06-07
申请号：US10295400
申请日：2002-11-14
IPC分类号： H01L21/316 , H01L21/336 , H01L29/49 , H01L29/786 , H01L21/00 , H01L21/84
CPC分类号： H01L29/66757 , H01L29/4908 , H01L29/66772
摘要： An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.
摘要翻译： 提供氧化物界面和制造氧化物界面的方法。 该方法包括形成硅层和覆盖硅层的氧化物层。 使用电感耦合等离子体源在低于400℃的温度下形成氧化物层。 在该方法的一些方面，氧化物层的厚度大于20纳米（nm），折射率在1.45和1.47之间。 在该方法的一些方面，通过等离子体氧化硅层形成氧化物层，以每分钟高达约4.4nm的速率产生等离子体氧化物（1分钟后）。 在该方法的某些方面，使用高密度等离子体增强化学气相沉积（HD-PECVD）工艺来形成氧化物层。 在该方法的一些方面，将硅和氧化物层结合到薄膜晶体管中。
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