公开(公告)号：US06995089B2

公开(公告)日：2006-02-07

申请号：US10434741

申请日：2003-05-08

申请人： Shih-Wei Chou ,  Minghsing Tsai ,  Winston Shue

发明人： Shih-Wei Chou ,  Minghsing Tsai ,  Winston Shue

IPC分类号： H01L21/302

CPC分类号： H01L21/32115 ,  B23H5/08 ,  C23F1/18 ,  C25F3/02 ,  H01L21/32134 ,  H01L21/7684 ,  H05K3/06 ,  H05K3/07 ,  H05K3/107 ,  H05K2203/0353 ,  H05K2203/1476

摘要： A new method is provided that allows for the application of electropolish for removal of copper and that is independent of pattern density of the removed copper. Electropolish of the copper is first accomplished by reversing current in the H2SO4 or H3PO4 solution. After identifying the endpoint of the electropolish, chemical etching of the copper in a H2SO4 or H3PO4 solution is continued, in this manner avoiding effects of high current density introduced by pattern density.

摘要翻译： 提供了一种新的方法，其允许使用电解抛光以除去铜，并且不依赖于去除的铜的图案密度。 铜的电解抛光首先通过在H 2 SO 3 / SO 3 H 4 SO 3 / SO 3 H 4 O 3 / 。 在鉴定了电解抛光物质的终点之后，在H 2 SO 3或4 H 3 PO 4中的铜的化学蚀刻， 继续以这种方式避免由图案密度引入的高电流密度的影响。

公开(公告)号：US08759975B2

公开(公告)日：2014-06-24

申请号：US13561826

申请日：2012-07-30

申请人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

发明人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L23/535

CPC分类号： H01L21/76856 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873

摘要： A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.

摘要翻译： 提供一种用于制造集成电路结构的方法和所得到的集成电路结构。 该方法包括形成低k电介质层; 在低k电介质层中形成开口; 形成覆盖所述低k电介质层的底部和侧壁的阻挡层; 在包括处理气体的环境中对阻挡层进行处理; 并用导电材料填充开口，其中导电材料在阻挡层上。

公开(公告)号：US20110241207A1

公开(公告)日：2011-10-06

申请号：US12753272

申请日：2010-04-02

申请人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

发明人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

IPC分类号： H01L23/52 ,  G06F17/50

CPC分类号： H01L21/76838 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

摘要翻译： 在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。 所公开的结构包括半导体衬底和衬底上方的材料层。 材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。 虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。

公开(公告)号：US20090111234A1

公开(公告)日：2009-04-30

申请号：US12316956

申请日：2008-12-17

申请人： Chun-Hong Chen ,  Minghsing Tsai

发明人： Chun-Hong Chen ,  Minghsing Tsai

IPC分类号： H01L21/20

CPC分类号： H01L23/5223 ,  H01L23/53228 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a metal-insulator-metal capacitor in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.

摘要翻译： 在多电平半导体器件中形成金属 - 绝缘体 - 金属电容器的方法利用半导体器件的铜互连电平作为电容器的一部分。 下电容器板由铜互连层和通过选择性沉积方法形成在铜互连层上的第一金属层组成。 上部电容器板包括与电容器电介质相同的图案，该图案具有小于下部电容器板的面积的面积。 上部电容器板由第二金属层形成。 第一和第二金属层可以各自由钴，钨，镍，钼或上述元素之一与硼和/或磷的组合形成。 导电通孔提供从上电容器板和下电容器板到互连电平的接触。

公开(公告)号：US07446047B2

公开(公告)日：2008-11-04

申请号：US11061350

申请日：2005-02-18

申请人： Minghsing Tsai ,  Yung-Cheng Lu

发明人： Minghsing Tsai ,  Yung-Cheng Lu

IPC分类号： H01L21/311

CPC分类号： H01L21/76834 ,  H01L21/02118 ,  H01L21/0226 ,  H01L21/3127 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835

摘要： A passivated metal structure and a method of forming the metal structure is disclosed. According to one embodiment, the patterned metal structure, such as conductive lines, are formed on a substrate. The copper lines are passivated by a polymer liner between the copper lines and a low k dielectric filling the spaces between the conductive lines. The polymer liner is preferably deposited on the sidewalls of the conductive lines by electro-grafting. The polymer liner may also be used in a damascene process according to a second embodiment.

摘要翻译： 公开了钝化金属结构和形成金属结构的方法。 根据一个实施例，图案化的金属结构，例如导电线，形成在基板上。 铜线由铜线之间的聚合物衬垫和填充导电线之间的空间的低k电介质钝化。 聚合物衬垫优选通过电接枝沉积在导电线的侧壁上。 聚合物衬垫也可以用于根据第二实施例的镶嵌工艺中。

公开(公告)号：US20070132061A1

公开(公告)日：2007-06-14

申请号：US11300567

申请日：2005-12-13

申请人： Chun-Hong Chen ,  Minghsing Tsai

发明人： Chun-Hong Chen ,  Minghsing Tsai

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： H01L23/5223 ,  H01L23/53228 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-insulator-metal capacitor formed in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.

摘要翻译： 形成在多电平半导体器件中的金属 - 绝缘体 - 金属电容器利用半导体器件的铜互连电平作为电容器的部分。 下电容器板由铜互连层和通过选择性沉积方法形成在铜互连层上的第一金属层组成。 上部电容器板包括与电容器电介质相同的图案，该图案具有小于下部电容器板的面积的面积。 上部电容器板由第二金属层形成。 第一和第二金属层可以各自由钴，钨，镍，钼或上述元素之一与硼和/或磷的组合形成。 导电通孔提供从上电容器板和下电容器板到互连电平的接触。

公开(公告)号：US06555474B1

公开(公告)日：2003-04-29

申请号：US10060820

申请日：2002-01-29

申请人： Cheng Lin Huang ,  Minghsing Tsai ,  Winston Shue ,  Mong-Song Liang

发明人： Cheng Lin Huang ,  Minghsing Tsai ,  Winston Shue ,  Mong-Song Liang

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76873

摘要： A method of forming a protective layer included in a metal filled semiconductor feature including providing a substrate including an insulating dielectric material having an anisotropically etched opening for forming a semiconductor feature; conformally depositing over the semiconductor feature at least one metal layer to substantially fill the semiconductor feature at least a portion of the at least one metal layer containing dopant impurities; and, thermally treating the substrate for a time period sufficient to redistribute the dopant impurities to preferentially collect along the periphery of the at least one metal layer.

摘要翻译： 一种形成包含在金属填充的半导体特征中的保护层的方法，包括提供包括具有用于形成半导体特征的各向异性蚀刻开口的绝缘介电材料的基板; 在所述半导体特征上共形沉积至少一个金属层以基本上填充所述至少一部分所述至少一个含有掺杂杂质的金属层的所述半导体特征; 并且将衬底热处理足以重新分布掺杂剂杂质的时间段，以优先地沿着至少一个金属层的周边收集。

公开(公告)号：US08623760B2

公开(公告)日：2014-01-07

申请号：US13440704

申请日：2012-04-05

申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

IPC分类号： H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。

公开(公告)号：US20130157462A1

公开(公告)日：2013-06-20

申请号：US13328680

申请日：2011-12-16

申请人： Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai ,  Syun-Ming Jang

发明人： Chia Ying Lee ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Minghsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/28 ,  H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32

摘要： The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.

公开(公告)号：US20120292767A1

公开(公告)日：2012-11-22

申请号：US13561826

申请日：2012-07-30

申请人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

发明人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L23/535

CPC分类号： H01L21/76856 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873

摘要： A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.

摘要翻译： 提供一种用于制造集成电路结构的方法和所得到的集成电路结构。 该方法包括形成低k电介质层; 在低k电介质层中形成开口; 形成覆盖所述低k电介质层的底部和侧壁的阻挡层; 在包括处理气体的环境中对阻挡层进行处理; 并用导电材料填充开口，其中导电材料在阻挡层上。