公开(公告)号：US11626146B1

公开(公告)日：2023-04-11

申请号：US17455292

申请日：2021-11-17

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam

IPC: G11C7/10 ,  G11C5/14

Abstract: The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

公开(公告)号：US11127896B2

公开(公告)日：2021-09-21

申请号：US16251230

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Frederick Mancoff ,  Sumio Ikegawa

IPC: H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.

公开(公告)号：US10658013B2

公开(公告)日：2020-05-19

申请号：US16252067

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Frederick Neumeyer

IPC: G11C5/14 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22 ,  G11C29/02 ,  G11C29/50

Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.

公开(公告)号：US10657065B2

公开(公告)日：2020-05-19

申请号：US16359514

申请日：2019-03-20

Applicant: Everspin Technologies, Inc.

Inventor： Thomas S. Andre ,  Syed M. Alam ,  Chitra K. Subramanian ,  Javed S. Barkatullah

IPC: G06F12/00 ,  G06F12/0893 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/0862 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32 ,  G11C11/16 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0846 ,  G06F12/0855

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US10395699B2

公开(公告)日：2019-08-27

申请号：US14496984

申请日：2014-09-25

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C7/12 ,  G11C7/06 ,  G11C5/06

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portion of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portions of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

公开(公告)号：US20190147971A1

公开(公告)日：2019-05-16

申请号：US16242892

申请日：2019-01-08

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G11C29/50 ,  G06F11/10 ,  G06F11/08 ,  G11C11/16

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US20180322918A1

公开(公告)日：2018-11-08

申请号：US15840214

申请日：2017-12-13

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang

IPC: G11C11/56 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L27/11 ,  G11C11/419

CPC classification number: G11C11/5607 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/419 ,  G11C2013/0071 ,  H01L27/11 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state. After the source of the selection transistor has been raised, the gate voltage of the selection transistor can also be raised at least as much as the source of the selection transistor has been elevated without violating the limits on the gate-to-source voltage for the selection transistor.

公开(公告)号：US20180267899A1

公开(公告)日：2018-09-20

申请号：US15986167

申请日：2018-05-22

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian ,  Javed S. Barkatullah

IPC: G06F12/0893 ,  G06F3/06 ,  G11C7/10 ,  G06F12/0802 ,  G11C11/16 ,  G11C16/32 ,  G11C7/22 ,  G06F12/0862

CPC classification number: G06F12/0893 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0215 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2024 ,  G06F2212/3042 ,  G06F2212/6026 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/1693 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2207/2272 ,  Y02D10/13

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US09697880B2

公开(公告)日：2017-07-04

申请号：US15193010

申请日：2016-06-25

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.

公开(公告)号：US09697879B2

公开(公告)日：2017-07-04

申请号：US15366083

申请日：2016-12-01

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Chitra K. Subramanian

IPC: G11C7/02 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

Abstract: In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared N-MOS and P-MOS followers used to apply read voltages across the bit cell and resistive circuit.