公开(公告)号：US09064932B1

公开(公告)日：2015-06-23

申请号：US14268478

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Zhenyu Hu

IPC: H01L21/70 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L21/76838 ,  H01L21/76865 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42316 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795

Abstract: One method disclosed includes, among other things, forming an uncut line-type gate structure above first and second spaced-apart active regions of a semiconductor substrate, forming a sidewall spacer around a perimeter of the line-type gate structure, performing at least one etching process to remove an axial portion of a gate cap layer and an axial portion of a gate electrode that are positioned above the isolation region so as to thereby define first and second cut end surfaces of first and second gate electrodes, respectively, and an isolation plug cavity and forming a gate cut isolation plug in the isolation plug cavity.

Abstract translation: 所公开的一种方法包括在半导体衬底的第一和第二间隔开的有源区之上形成未切割线型栅极结构，在线型栅极结构的周边上形成侧壁隔离物，执行至少一个 蚀刻工艺以去除位于隔离区域上方的栅极盖层和栅电极的轴向部分的轴向部分，从而分别限定第一和第二栅电极的第一和第二切割端表面，以及隔离 插塞腔并在隔离插塞腔中形成栅极切割隔离插头。

公开(公告)号：US20200243646A1

公开(公告)日：2020-07-30

申请号：US16262105

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  George R. Mulfinger ,  Hui Zang ,  Liu Jiang ,  Zhenyu Hu

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.

公开(公告)号：US20200020770A1

公开(公告)日：2020-01-16

申请号：US16033812

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu ,  George R. Mulfinger

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: Structures for field-effect transistors and methods for forming field-effect transistors. A sidewall spacer is arranged adjacent to a sidewall of a gate structure. The sidewall spacer includes a first section and a second section arranged over the first section. The first section of the sidewall spacer is composed of a first dielectric material, and the second section of the sidewall spacer is composed of a second dielectric material different from the first dielectric material. A source/drain region includes a first section arranged adjacent to the first section of the sidewall spacer and a second section arranged adjacent to the second section of the sidewall spacer. The second section of the source/drain region is spaced by a gap from the second section of the sidewall spacer.

公开(公告)号：US10475890B2

公开(公告)日：2019-11-12

申请号：US15728070

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hui Zang ,  Hong Yu ,  Zhenyu Hu ,  Scott Beasor ,  Erik Geiss ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

公开(公告)号：US10396206B2

公开(公告)日：2019-08-27

申请号：US15643940

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar Jha ,  Haiting Wang ,  Wei Hong ,  Wei Zhao ,  Tae Jeong Lee ,  Zhenyu Hu

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/475 ,  H01L29/43 ,  H01L27/02 ,  H01L27/118

Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.

公开(公告)号：US10326002B1

公开(公告)日：2019-06-18

申请号：US16004935

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Scott Beasor ,  Zhenyu Hu

IPC: H01L29/02 ,  H01L29/778 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/417

Abstract: Methods of forming self-aligned gate contacts and cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include self-aligned gate contacts and cross-coupling contacts. A sidewall spacer is formed at a sidewall of a gate structure and an epitaxial semiconductor layer is formed adjacent to the sidewall spacer. After forming the epitaxial semiconductor layer, the sidewall spacer is recessed with a first etching process. After recessing the spacer, the gate structure is recessed with a second etching process. After recessing the gate structure, a cross-coupling contact is formed that connects the gate structure with the epitaxial semiconductor layer.

公开(公告)号：US20190035633A1

公开(公告)日：2019-01-31

申请号：US15665183

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ashish Kumar Jha ,  Hui Zhan ,  Hong Yu ,  Zhenyu Hu ,  Haiting Wang ,  Edward Reis ,  Charles Vanleuvan

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/475

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material. An isotropic Fin reveal process is performed and the STI structure assists in equalizing fin heights and increasing active S/D region area/volume.

公开(公告)号：US10090382B1

公开(公告)日：2018-10-02

申请号：US15811957

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Xinyuan Dou ,  Hui Zhan ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L27/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/027

Abstract: The disclosure relates to forming single diffusion break (SDB) and end isolation regions in an integrated circuit (IC) structure, and resulting structures. An IC structure according to the disclosure includes: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of gate structures; at least one single diffusion break (SDB) region positioned within the insulator region and one of the plurality of fins, the at least one SDB extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of gate structures.

公开(公告)号：US10043713B1

公开(公告)日：2018-08-07

申请号：US15591814

申请日：2017-05-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan Dou ,  Hong Yu ,  Zhenyu Hu ,  Xing Zhang

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423

Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.

公开(公告)号：US09947769B1

公开(公告)日：2018-04-17

申请号：US15363461

申请日：2016-11-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6656 ,  H01L21/0214 ,  H01L21/0228 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer is located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer is located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.