公开(公告)号：US20180175209A1

公开(公告)日：2018-06-21

申请号：US15384706

申请日：2016-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/3105 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor structure includes a support substrate including a semiconductor material, a buried insulation layer positioned above the support substrate, a semiconductor layer positioned above the buried insulation layer, the semiconductor layer having an upper surface and a lower surface, the lower surface being positioned on the buried insulation layer, and at least one nonvolatile memory cell. The nonvolatile memory cell includes a channel region, a front gate structure, a doped back gate region and a charge storage material. The channel region is located in the semiconductor layer. The front gate structure is located above the channel region and the upper surface of the semiconductor layer. The doped back gate region is located in the support substrate below the channel region. The charge storage material is embedded at least into a portion of the buried insulation layer between the channel region and the back gate region.

公开(公告)号：US09905707B1

公开(公告)日：2018-02-27

申请号：US15337026

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrei Sidelnicov ,  Alban Zaka ,  El Mehdi Bazizi ,  Venkata Naga Ranjith Kumar Nelluri ,  Juergen Faul

IPC: H01L29/00 ,  H01L29/94 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/94 ,  H01L21/265 ,  H01L29/66174

Abstract: Capacitive structures in the device level of sophisticated MOS devices may be formed so as to exhibit a significantly reduced capacitance/voltage variability. To this end, a highly doped semiconductor region may be formed in the “channel” of the capacitive structure. For example, for a specified concentration of the dopant species and a specified range of the vertical dimension of the highly doped semiconductor region, a reduced variability of approximately 3% or less may be obtained for a voltage range of, for example, ±5 V.

公开(公告)号：US20180053789A1

公开(公告)日：2018-02-22

申请号：US15799243

申请日：2017-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul

IPC: H01L27/12 ,  H01L27/02 ,  H01L23/50

CPC classification number: H01L27/1207 ,  H01L23/50 ,  H01L27/0288

Abstract: A method includes providing a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region. A semiconductor device is provided in the SOI region. The semiconductor device includes a gate structure, a diode structure provided in the hybrid region and coupled to a substrate material of the SOI region, a supply circuit arrangement including first and second supply lines, a first resistor coupled between the first supply line and a first terminal of the diode structure, and a second resistor coupled between the second supply line and the substrate material positioned beneath the gate structure. At least one of the first and second resistors comprises a tunable resistor. A resistance of the tunable resistor is adjusted so as to adjust a threshold voltage (Vt) of the semiconductor device in dependence on an operating temperature of the SOI region.

公开(公告)号：US09876111B2

公开(公告)日：2018-01-23

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

公开(公告)号：US20170250191A1

公开(公告)日：2017-08-31

申请号：US15053485

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/308 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/265 ,  H01L27/12 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11582 ,  H01L27/1207 ,  H01L28/00 ,  H01L29/42336 ,  H01L29/42352

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US20170170317A1

公开(公告)日：2017-06-15

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

公开(公告)号：US20150145061A1

公开(公告)日：2015-05-28

申请号：US14590076

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L27/11 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/66969

Abstract: A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region.

Abstract translation: 器件包括位于半导体衬底中的第一和第二间隔开的有源区，位于第一和第二间隔开的有源区之间的隔离区和位于第一有源区上的栅极绝缘材料层。 第一导线特征从第一有源区连续延伸并跨越隔离区到第二有源区，其中第一导线特征包括位于第一有源区上的栅极绝缘材料层正上方的第一部分， 以及与第二有源区域导电接触的第二部分。

公开(公告)号：US08956928B2

公开(公告)日：2015-02-17

申请号：US13689979

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L21/00 ,  H01L21/60 ,  H01L29/66 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/1104 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/66969

Abstract: One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region.

Abstract translation: 一个器件包括形成在半导体衬底中的第一和第二间隔开的有源区，位于第一有源区上的栅极绝缘材料层，和具有位于栅绝缘材料上方的第一部分的导线特征，以及第二部分 导电地接触第二活性区域。 一种方法包括在半导体衬底中形成第一和第二间隔开的有源区，在第一和第二有源区上形成栅极绝缘材料层，执行蚀刻工艺以去除形成在第二有源区上的栅极绝缘材料的一部分 区域以暴露第二有源区域的一部分，以及形成导线特征，其包括位于形成在第一有源区上的栅绝缘材料层之上的第一部分和与第二有源区的暴露部分导电接触的第二部分 地区。

公开(公告)号：US20150041910A1

公开(公告)日：2015-02-12

申请号：US13961554

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Stefan Flachowksy ,  Juergen Faul ,  Jan Hoentschel

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807

Abstract: Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions.

Abstract translation: 提供集成电路和制造集成电路的方法。 在示例性实施例中，集成电路包括轻掺杂有分为第一器件区域和第二器件区域的第一掺杂剂类型的体硅衬底，以及形成第二掺杂剂类型的轻掺杂阱区 在第二设备区域中。 集成电路还包括与第一栅极电极结构对准的第一掺杂剂类型的重掺杂源极/漏极延伸区域和与第二栅电极结构对准的第二掺杂剂类型的重掺杂源极/漏极延伸区域，并且中间地 形成在第一栅电极结构下方的第二掺杂剂类型的掺杂晕圈区域和位于第二栅电极结构下方的第一掺杂剂类型的中间掺杂卤区。 此外，集成电路包括重掺杂源极/漏极区域。

公开(公告)号：US08951920B2

公开(公告)日：2015-02-10

申请号：US14446797

申请日：2014-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L21/31 ,  H01L23/495

CPC classification number: H01L24/03 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2224/034 ,  H01L2224/03614 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A method of forming a conductive contact landing pad and a transistor includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, and performing an etching process to remove the layer of gate insulation material formed on the second active region so as to thereby expose the second active region. The method further includes performing a common process operation to form a gate electrode structure above the layer of gate insulation material on the first active region for the transistor and the conductive contact landing pad that is conductively coupled to the second active region, and forming a contact to the conductive contact landing pad.

Abstract translation: 形成导电接触着陆焊盘和晶体管的方法包括在半导体衬底中形成第一和第二间隔开的有源区，在第一和第二有源区上形成栅极绝缘材料层，并执行蚀刻工艺以去除 形成在第二有源区上的栅极绝缘材料层，从而露出第二有源区。 该方法还包括执行公共处理操作，以在晶体管的第一有源区上形成栅极绝缘材料层上方的栅电极结构，以及与第二有源区导电耦合的导电接触着陆焊盘，并形成接触 到导电接触着陆垫。