公开(公告)号：US09236463B2

公开(公告)日：2016-01-12

申请号：US14027563

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/10 ,  H01L29/205 ,  H01L29/20 ,  H01L29/51

CPC classification number: H01L29/778 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/205 ,  H01L29/4232 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

公开(公告)号：US10199220B2

公开(公告)日：2019-02-05

申请号：US15652413

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US10068920B2

公开(公告)日：2018-09-04

申请号：US15098722

申请日：2016-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Veeraraghavan S. Basker ,  Shogo Mochizuki ,  Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/324

Abstract: Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed. The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.

公开(公告)号：US20180190797A1

公开(公告)日：2018-07-05

申请号：US15911415

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/306 ,  H01L21/324 ,  H01L21/321 ,  H01L21/768

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US09793113B2

公开(公告)日：2017-10-17

申请号：US15075668

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/20 ,  H01L29/78 ,  H01L21/02 ,  H01L21/31 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/0243 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/31 ,  H01L21/311 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66446 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US20170148661A1

公开(公告)日：2017-05-25

申请号：US15425338

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L21/76 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.

公开(公告)号：US09601624B2

公开(公告)日：2017-03-21

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L29/167 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

公开(公告)号：US09601565B2

公开(公告)日：2017-03-21

申请号：US14578523

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L29/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778 ,  H01L21/02

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.

公开(公告)号：US09514995B1

公开(公告)日：2016-12-06

申请号：US14718760

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785

Abstract: A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Abstract translation: 通过使用掺杂氧化物的体积FinFET结构形成穿通停止层。 通过退火将掺杂剂驱入散热片的基板和基部。 穿通停止层包括p型区域和n型区域，它们都可以延伸到半导体鳍片中基本相等的距离。

公开(公告)号：US09401373B2

公开(公告)日：2016-07-26

申请号：US14641462

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate.