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    FinFET devices having recessed liner materials to define different fin heights
    34.
    发明授权
    FinFET devices having recessed liner materials to define different fin heights 有权
    FinFET器件具有凹陷的衬垫材料以限定不同的翅片高度

    公开(公告)号：US09000537B2

    公开(公告)日：2015-04-07

    申请号：US14333683

    申请日：2014-07-17

    Applicant: Globalfoundries Inc. ,  International Business Machines Corporation

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L27/0207 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

    Abstract: One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

    Abstract translation: 一种方法包括通过图案化的掩模层执行蚀刻工艺，以在限定第一和第二鳍片的衬底中形成沟槽，将邻近第一鳍片的衬垫材料形成第一厚度，将与第二鳍片相邻的衬垫材料形成为不同于第二厚度的第二厚度 所述第一厚度在所述沟槽中形成绝缘材料，所述沟槽邻近所述衬垫材料并且在所述掩模层上方，执行处理操作以去除所述绝缘材料层的部分并暴露所述衬垫材料的部分，执行另一蚀刻工艺以去除部分 所述衬垫材料和所述掩模层将所述第一翅片暴露于第一高度，并且所述第二鳍片具有不同于所述第一高度的第二高度，执行另一蚀刻工艺以限定绝缘材料的厚度减薄层，以及形成栅极结构 围绕第一和第二鳍的一部分。

    SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES
    35.
    发明申请
    SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES 有权
    用于FINFET器件的自对准介电隔离

    公开(公告)号：US20150061040A1

    公开(公告)日：2015-03-05

    申请号：US14538401

    申请日：2014-11-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

    Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L27/088 ,  H01L29/06

    CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

    Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

    Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

    METHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING
    36.
    发明申请
    METHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING 审中-公开
    通过现场掺杂分离Si的器件分离方法

    公开(公告)号：US20140374807A1

    公开(公告)日：2014-12-25

    申请号：US13921265

    申请日：2013-06-19

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce B. Doris ,  Ali Khakifirooz

    IPC: H01L29/78 ,  H01L21/02

    CPC classification number: H01L29/785 ,  H01L29/66803

    Abstract: Aspects of the present invention relate to an approach for forming an integrated circuit having a set of fins on a silicon substrate, with the set of fins being formed according to a predetermined pattern. In situ doping of the fins with an N-type dopant prior to deposition of an epitaxial layer minimizes punch through leakage whilst an epitaxial depositional process applies a cladding layer on the doped fins, the deposition resulting in a multigate device having improved device isolation.

    Abstract translation: 本发明的方面涉及一种用于形成在硅衬底上具有一组散热片的集成电路的方法，该散热片组根据预定图案形成。 在沉积外延层之前用N型掺杂剂原位掺杂散热片使冲击穿孔最小化，而外延沉积工艺在掺杂的翅片上施加覆层，沉积导致具有改进的器件隔离的多器件装置。

    METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE
    37.
    发明申请
    METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE 有权
    通过使用真实内衬和结果设备来增加接触元件空间的方法

    公开(公告)号：US20140264479A1

    公开(公告)日：2014-09-18

    申请号：US13797001

    申请日：2013-03-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

    IPC: H01L29/40 ,  H01L29/417

    CPC classification number: H01L29/401 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

    Abstract: One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least portions of the second liner layer relative to the first liner layer, forming a second layer of insulating material above the first layer of insulating material, performing at least one second etching process to remove at least portions of the first and second layers of insulating material and at least portions of the first liner layer so as to thereby expose an outer surface of the sidewall spacer, and forming a conductive contact that contacts the exposed outer surface of the sidewall spacer and a source/drain region of the transistor.

    Abstract translation: 一种方法包括在栅极结构附近形成侧壁间隔物，在侧壁间隔物上形成第一衬里层，在第一衬里层上形成第二衬里层，在衬底上方形成第一绝缘材料层并邻近第二衬层， 选择性地去除所述第二衬层的至少部分相对于所述第一衬层，在所述第一绝缘材料层之上形成第二绝缘材料层，执行至少一个第二蚀刻工艺以移除所述第一层和所述第二层的至少一部分 的绝缘材料和第一衬里层的至少部分，从而暴露侧壁间隔件的外表面，并且形成接触暴露的侧壁间隔物的外表面和晶体管的源极/漏极区域的导电接触。

    Prevention of fin erosion for semiconductor devices
    38.
    发明授权
    Prevention of fin erosion for semiconductor devices 有权
    防止半导体器件的翅片侵蚀

    公开(公告)号：US08809920B2

    公开(公告)日：2014-08-19

    申请号：US13670674

    申请日：2012-11-07

    Applicant: International Business Machines Corporation ,  GlobalFoundries Inc.

    Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L29/76

    CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

    Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

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