公开(公告)号：US06845554B2

公开(公告)日：2005-01-25

申请号：US10298837

申请日：2002-11-18

申请人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H01L21/00 ,  H01L21/60 ,  H01L21/78 ,  H05K3/30

CPC分类号： H01L24/96 ,  H01L21/67144 ,  H01L21/78 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49135 ,  Y10T29/49155 ,  Y10T29/53178

摘要： The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, the functional circuit units (101d) are picked up by means of a handling device (101) and are placed down on a second film (102b) by means of the handling device (103), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units (101d).

摘要翻译： 本发明创造了一种用于连接电路单元（101a-10n）的方法，它们布置在晶片（100）上，其中晶片（100）装配到第一薄膜（102a）上，晶片（100）被锯切 布置在晶片（100）上的电路单元（101a-101n）被分离，功能电路单元（101d）通过处理装置（101）拾取并放置在第二薄膜（102b）上 ），以便产生可以在电路单元（101d）的连接触点之间预定的间隔距离。

公开(公告)号：US06649999B2

公开(公告)日：2003-11-18

申请号：US10187766

申请日：2002-07-02

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： H01L2900

CPC分类号： H01L23/5223 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

摘要： In a semiconductor chip, conductive tracks run in a rewiring layer from contact pads to contact elevations. The contact pads are formed as vias. The conductive tracks are constructed in sections as bottom electrodes of trimming capacitors. The top electrode of the trimming capacitors is formed by a metal plane of the rewiring layer.

摘要翻译： 在半导体芯片中，导电轨迹在接线层中从接线层延伸到接触高度。 接触垫形成为通孔。 导电轨道被构造为微调电容器的底部电极。 修整电容器的顶部电极由重新布线层的金属平面形成。

公开(公告)号：US06580613B2

公开(公告)日：2003-06-17

申请号：US09907894

申请日：2001-07-17

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： H05K720

CPC分类号： H01L24/90 ,  H01L23/32 ,  H01L23/3672 ,  H01L24/72 ,  H01L25/0652 ,  H01L2224/10165 ,  H01L2224/16227 ,  H01L2224/73251 ,  H01L2224/81901 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/19043 ,  H05K3/325 ,  H01L2224/16 ,  H01L2224/72

摘要： An electronic component assembly is disclosed. The electronic component assembly may comprise a printed circuit board, a frame secured to the printed circuit board and one or more electronic components mounted in the frame and arranged in electrical contact with conductive traces of the printed circuit board, wherein no solder is used to connect the electronic components to the printed circuit board. A method for assembling the electronic component assembly is also disclosed.

摘要翻译： 公开了一种电子部件组件。 电子部件组件可以包括印刷电路板，固定到印刷电路板的框架和安装在框架中并且布置成与印刷电路板的导电迹线电接触的一个或多个电子部件，其中不使用焊料来连接 电子元件到印刷电路板。 还公开了一种用于组装电子部件组件的方法。

公开(公告)号：US07434125B2

公开(公告)日：2008-10-07

申请号：US11415443

申请日：2006-05-01

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G01R31/28

CPC分类号： G11C29/26 ,  G11C2029/2602

摘要： An integrated circuit is provided, the integrated circuit having a test circuit for reading out an error datum from the integrated circuit in accordance with a test mode, wherein the error datum is output via a first and a second data output, and wherein an address and a read command are applied to the integrated circuit to read out the error datum associated with the address via one of the data outputs. The test circuit is configured in such a manner that, when a first read command is applied, the test circuit outputs the error datum at the first data output and switches the second data output to high impedance and, when a second read command is applied, the test circuit outputs the error datum at the second data output and switches the first data output to high impedance.

摘要翻译： 提供了一种集成电路，该集成电路具有用于根据测试模式从集成电路读出错误数据的测试电路，其中该误差数据经由第一和第二数据输出被输出，并且其中一个地址和 读取命令被应用于集成电路，以通过数据输出之一读出与地址相关联的错误数据。 测试电路被配置成使得当应用第一读取命令时，测试电路在第一数据输出处输出误差数据并将第二数据输出切换为高阻抗，并且当应用第二读取命令时， 测试电路在第二个数据输出端输出误差数据，并将第一个数据输出切换到高阻抗。

公开(公告)号：US07331005B2

公开(公告)日：2008-02-12

申请号：US11189231

申请日：2005-07-26

申请人： Ralf Arnold ,  Gerd Frankowsky ,  Wolfgang Spirkl

发明人： Ralf Arnold ,  Gerd Frankowsky ,  Wolfgang Spirkl

IPC分类号： G01R31/28 ,  G06K5/04 ,  G06F11/00

CPC分类号： G01R31/3016

摘要： Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.

摘要翻译： 用于测试半导体器件的方法和装置。 测试接口被配置为与外部测试设备和被测设备（DUT）接口。 在一个实施例中，测试接口从外部测试装置接收测试数据和测试时钟信号。 测试数据根据测试时钟信号从测试接口输出到DUT。 此外，测试时钟信号被延迟一段时间，然后向设备发出延迟的时钟信号。 先前写入DUT的数据从DUT读出并与从外部测试装置接收的测试数据进行比较。 可以改变测试时钟信号被延迟的时间段以实现期望的时序。

公开(公告)号：US07061260B2

公开(公告)日：2006-06-13

申请号：US10894942

申请日：2004-07-20

申请人： Gerd Frankowsky ,  Thorsten Bucksch ,  Gerd Brösamlen

发明人： Gerd Frankowsky ,  Thorsten Bucksch ,  Gerd Brösamlen

IPC分类号： G01R31/02

CPC分类号： G01R31/3191 ,  G01R31/31905

摘要： A calibration device for the calibration of a tester channel of a tester device is provided. The calibration device includes a connecting device and a planar contact carrier with a first contact area and a second contact area insulated from the first contact area, the first contact area being generally surrounded by the second contact area, so that, when a needle card connected to the tester device is placed onto the contact carrier of the calibration device, one of the contact-connecting needles of the needle card which is connected to the tester channel to be calibrated is placed onto the first contact area and a plurality or all of the further contact-connecting needles of the needle card at tester channels that are not to be calibrated are placed onto the second contact area.

摘要翻译： 提供了用于校准测试器设备的测试器通道的校准装置。 校准装置包括连接装置和具有与第一接触区域绝缘的第一接触区域和第二接触区域的平面接触载体，第一接触区域通常被第二接触区域包围，使得当针卡连接 将测试器装置放置在校准装置的接触载体上，连接到要校准的测试器通道的针卡的接触连接针中的一个被放置在第一接触区域上，并且多个或全部 在未被校准的测试器通道处的针卡的另外的接触连接针被放置在第二接触区域上。

公开(公告)号：US06717870B2

公开(公告)日：2004-04-06

申请号：US10185282

申请日：2002-06-27

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G11C700

CPC分类号： G11C29/006 ,  G11C29/44

摘要： Assessing the burn-in of faulty memory units on a wafer includes detecting only those defective memory cells that lie along control lines in the case of which the total number of defective memory cells does not exceed a predetermined limit value. With such a quality criterion, it is also possible to monitor the burn-in of faulty memory units on a wafer.

摘要翻译： 评估晶片上的故障存储器单元的老化包括仅在缺陷存储器单元的总数不超过预定极限值的情况下仅检测位于控制线上的那些有缺陷的存储器单元。 通过这样的质量标准，还可以监视晶片上的故障存储器单元的老化。

公开(公告)号：US06483764B2

公开(公告)日：2002-11-19

申请号：US09761045

申请日：2001-01-16

申请人： Louis Lu Chen Hsu ,  Gerd Frankowsky ,  Oliver Weinfurtner

发明人： Louis Lu Chen Hsu ,  Gerd Frankowsky ,  Oliver Weinfurtner

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C2207/104 ,  G11C2207/2254

摘要： A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized. The advantages of this method over the existing method, that is, adjusting the refresh cycle time based on chip temperature include (1) the contributions from non-temperature dependent leakage factors are taken into consideration, (2) the present invention does not require different process steps, or extra process costs to integrate such device in the chip, and (3) the present invention is a straight forward method, the monitor cell does not need any calibration. In addition, its leakage mechanism and reliability concern are all identical to the cells in a real array.

摘要翻译： 一种新颖的DRAM刷新方法和系统以及设计低功耗漏电监测装置的新方法。 利用DRAM刷新方法，基于单元泄漏状况来调整时间。 设计低功率泄漏监测装置的方法使用与真实阵列中的单元相同的存储单元。 该监视器单元被设计成它将代表平均单元或最坏的单元泄漏状况。 如果泄漏严重，则刷新周期时间会显着减少或减半。 如果泄漏电平非常低或不可检测，则刷新周期时间显着增加或加倍。 如果泄漏中等或在正常范围内，则刷新时间被优化，使得用于DRAM刷新的功耗最小化。 该方法优于现有方法，即基于芯片温度调整刷新周期时间的优点包括：（1）考虑到非温度依赖性泄漏因素的贡献，（2）本发明不需要不同的 处理步骤或额外的处理成本，以及（3）本发明是一种直接的方法，监测单元不需要任何校准。 此外，其泄漏机制和可靠性问题与实际阵列中的单元格完全相同。

公开(公告)号：US06262615B1

公开(公告)日：2001-07-17

申请号：US09257304

申请日：1999-02-25

申请人： Toshiaki Kirihata ,  Gerd Frankowsky

发明人： Toshiaki Kirihata ,  Gerd Frankowsky

IPC分类号： H03K3037

CPC分类号： G11C19/28 ,  G11C7/1048 ,  G11C19/00 ,  H03K19/0963

摘要： A dynamic logic circuit having a charging circuit, comprising a first transistor having a first source/drain electrode adapted for coupling to a voltage supply and a second source/drain electrode connected to a node. The charging circuit couples the voltage supply to the node to place an initial charge on the node. A data transfer circuit is provided comprising a second transistor having a gate adapted for coupling to an input strobe pulse, a first source/drain electrode connected to the node, and a second source/drain electrode responsive to an input data and the input strobe pulse, for transferring the input data to the node to the node such that the pre-charged node is either discharged or remains depending on the input data. An output circuit is responsive to an output strobe pulse for coupling the data at the node to an output. A trailing edge detector of the output strobe pulse detects a time at which the coupling of the data to the output is complete and pre-charges the node at a high level for a subsequent input strobe pulse.

摘要翻译： 一种具有充电电路的动态逻辑电路，包括具有适于耦合到电压源的第一源极/漏极电极和连接到节点的第二源极/漏极电极的第一晶体管。 充电电路将电压源耦合到节点以在节点上放置初始电荷。 提供了一种数据传输电路，包括具有适于耦合到输入选通脉冲的栅极的第二晶体管，连接到该节点的第一源极/漏极电极和响应于输入数据和输入选通脉冲的第二源极/漏极电极 用于将输入数据传送到节点到节点，使得预充电节点根据输入数据被放电或保持。 输出电路响应于输出选通脉冲，用于将节点处的数据耦合到输出。 输出选通脉冲的后沿检测器检测数据到输出的耦合完成的时间，并且为了后续的输入选通脉冲将节点预充电到高电平。

公开(公告)号：US20080059102A1

公开(公告)日：2008-03-06

申请号：US11469365

申请日：2006-08-31

申请人： Gerd Frankowsky ,  Roman Mayr

发明人： Gerd Frankowsky ,  Roman Mayr

IPC分类号： G06F19/00

CPC分类号： G11C29/38 ,  G01R31/31937 ,  G11C29/022 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/5002

摘要： A system and method for testing an integrated circuit is provided. In one embodiment, a method includes comparing the signal level of the output signal of the integrated circuit to the signal level of a reference signal, wherein a comparison signal is output, which has a first or a second value depending on whether the actual signal level of the output signal is above or below the actual signal level of the reference signal; determining the value of the comparison signal at a certain time; evaluating the value of the comparison signal determined at the time by way of a default; and outputting an error signal if the determined value of the comparison signal does not correspond to the default.

摘要翻译： 提供了一种用于测试集成电路的系统和方法。 在一个实施例中，一种方法包括将集成电路的输出信号的信号电平与参考信号的信号电平进行比较，其中输出比较信号，其具有取决于实际信号电平的第一或第二值 的输出信号高于或低于参考信号的实际信号电平; 在一定时间确定比较信号的值; 通过默认方式评估当时确定的比较信号的值; 如果比较信号的确定值不对应于默认值，则输出错误信号。