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68 条记录 (耗时 0.018 秒)

    Electrically programmable non-volatile memory cell configuration
    31.
    发明授权
    Electrically programmable non-volatile memory cell configuration 有权
    电可编程非易失性存储单元配置

    公开(公告)号：US06215140B1

    公开(公告)日：2001-04-10

    申请号：US09398691

    申请日：1999-09-20

    申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC分类号： H01L2972

    CPC分类号： H01L21/8229 ,  H01L27/1021

    摘要： A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

    摘要翻译： 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

    Method for fabricating a dopant region
    32.
    发明授权
    Method for fabricating a dopant region 有权
    掺杂剂区域的制造方法

    公开(公告)号：US6133126A

    公开(公告)日：2000-10-17

    申请号：US398688

    申请日：1999-09-20

    申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC分类号： H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

    CPC分类号： H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

    摘要： A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

    摘要翻译： 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。

    CMOS-compatible bipolar transistor with reduced collector/substrate capacitance and process for producing the same
    34.
    发明授权
    CMOS-compatible bipolar transistor with reduced collector/substrate capacitance and process for producing the same 失效
    具有降低的集电极/衬底电容的CMOS兼容双极晶体管及其制造方法

    公开(公告)号：US5177582A

    公开(公告)日：1993-01-05

    申请号：US754377

    申请日：1991-08-30

    申请人： Thomas Meister ,  Hans-Willi Meul ,  Helmut Klose ,  Hermann Wendt

    发明人： Thomas Meister ,  Hans-Willi Meul ,  Helmut Klose ,  Hermann Wendt

    IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/732

    CPC分类号： H01L29/0826 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/732

    摘要： A bipolar transistor with a collector, a base and an emitter disposed in vertical succession includes a semiconductor substrate, insulating oxide zones disposed in the substrate for separating adjacent transistors, and a buried collector terminal layer at least partly disposed on the insulating oxide zones. An insulator structure laterally surrounding a collector. A subcollector is surrounded by the insulating oxide zones, has the same conductivity type with a lower impedance than the collector, is disposed under the collector and under the insulator structure, and is electrically connected to the collector. The insulator structure covers the buried collector terminal layer, laterally insulates the collector from the buried collector terminal layer, and has lateral surfaces extending inside the insulating oxide regions up to the subcollector. The buried collector terminal layer is in direct contact with the subcollector. The collector is electrically connected to the buried collector terminal layer only through the subcollector. The insulator structure has a contact hole extending to the buried collector terminal layer laterally of the active transistor zone, and a metallization filling the contact hole. A process for producing the bipolar transistor includes producing an insulator structure on a substrate for determining a location for a collector; and producing the collector by selective epitaxy only inside the insulator structure, for laterally insulating the collector with the insulator structure. An integrated circuit and method include such bipolar transistors and CMOS transistors.

    摘要翻译： 具有垂直相继布置的集电极，基极和发射极的双极晶体管包括半导体衬底，设置在衬底中用于分离相邻晶体管的绝缘氧化物区域和至少部分地设置在绝缘氧化物区域上的埋地集电极端子层。 横向围绕收集器的绝缘体结构。 子集电极被绝缘氧化物区围绕，具有与集电体相比具有较低阻抗的相同的导电类型，设置在集电器下方和绝缘体结构下方，并且与集电极电连接。 绝缘体结构覆盖埋地集电极端子层，使集电体与埋地集电极端子层横向绝缘，并且具有在绝缘氧化物区域内延伸直到子集电极的侧表面。 埋地集电极端子层与子集电极直接接触。 集电极仅通过子集电极电连接到埋地集电极端子层。 绝缘体结构具有在有源晶体管区域侧向延伸到集电极端子层的接触孔，以及填充接触孔的金属化。 制造双极晶体管的方法包括：在基板上制造用于确定集电体位置的绝缘体结构; 并且仅通过绝缘体结构内的选择性外延生产集电体，用于使绝缘体结构的集电体横向绝缘。 集成电路和方法包括这样的双极晶体管和CMOS晶体管。

    Integration scheme for fully silicided gate
    37.
    发明授权
    Integration scheme for fully silicided gate 有权
    完全硅化栅的集成方案

    公开(公告)号：US07544553B2

    公开(公告)日：2009-06-09

    申请号：US11094367

    申请日：2005-03-30

    申请人： Marcus Culmsee ,  Hermann Wendt ,  Lothar Doni

    发明人： Marcus Culmsee ,  Hermann Wendt ,  Lothar Doni

    IPC分类号： H01L23/336 ,  H01L21/3205

    CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L29/66545 ,  H01L29/6656

    摘要： To form a semiconductor device, a silicon (e.g., polysilicon) gate layer is formed over a gate dielectric and a sacrificial layer (preferably titanium nitride) is formed over the silicon gate layer. The silicon gate layer and the sacrificial layer are patterned to form a gate structure. A spacer, such as an oxide sidewall spacer and a nitride sidewall spacer, is formed adjacent the sidewall of the gate structure. The semiconductor body is then doped to form a source region and a drain region that are self-aligned to the spacers. The sacrificial layer can then be removed selectively with respect to the oxide sidewall spacer, the nitride sidewall spacer and the silicon gate. A metal layer (e.g., nickel) is formed over the source region, the drain region and the silicon gate and reacted with these regions to form a silicided source contact, a silicided drain contact and a silicided gate.

    摘要翻译： 为了形成半导体器件，在栅极电介质上形成硅（例如，多晶硅）栅极层，并且在硅栅极层上形成牺牲层（优选氮化钛）。 图案化硅栅极层和牺牲层以形成栅极结构。 邻近栅极结构的侧壁形成间隔物，例如氧化物侧壁间隔物和氮化物侧壁间隔物。 然后，半导体体被掺杂以形成与间隔物自对准的源极区域和漏极区域。 然后可以相对于氧化物侧壁间隔物，氮化物侧壁间隔物和硅栅极选择性地去除牺牲层。 在源极区域，漏极区域和硅栅极上形成金属层（例如镍），并与这些区域反应以形成硅化物源极接触，硅化物漏极接触和硅化物栅极。

    Method for producing a layer arrangement
    38.
    发明申请
    Method for producing a layer arrangement 有权
    层布置方法

    公开(公告)号：US20080102625A1

    公开(公告)日：2008-05-01

    申请号：US11639393

    申请日：2006-12-14

    申请人： Stefan Eckert ,  Klaus Goller ,  Hermann Wendt

    发明人： Stefan Eckert ,  Klaus Goller ,  Hermann Wendt

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L21/76834

    摘要： The invention relates to a method for producing a layer arrangement. An electrically conductive layer is formed and patterned. A sacrificial layer formed on at least part of the patterned electrically conductive layer. An electrically insulating layer is formed on the electrically conductive and sacrificial layers and is patterned in such a manner that one or more surface areas of the sacrificial layer are exposed. The exposed areas of the sacrificial layer are removed to expose one or more surface areas of the patterned electrically conductive layer. The patterned electrically conductive layer is covered with a pattern of electrically conductive material.

    摘要翻译： 本发明涉及一种生产层布置的方法。 形成导电层并构图。 形成在图案化导电层的至少一部分上的牺牲层。 在导电和牺牲层上形成电绝缘层，并以牺牲层的一个或多个表面区域露出的方式构图。 去除牺牲层的暴露区域以暴露图案化导电层的一个或多个表面区域。 图案化的导电层被导电材料的图案覆盖。