利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

91 条记录 (耗时 0.025 秒)

    Plasma reactor and processes using RF inductive coupling and scavenger temperature control
    31.
    发明授权
    Plasma reactor and processes using RF inductive coupling and scavenger temperature control 失效
    等离子体反应器和使用射频感应耦合和清除温度控制的工艺

    公开(公告)号：US5888414A

    公开(公告)日：1999-03-30

    申请号：US936777

    申请日：1997-09-24

    申请人： Kenneth S. Collins ,  Chan-Lon Yang ,  Jerry Yuen-Kui Wong ,  Jeffrey Marks ,  Peter R. Keswick ,  David W. Groechel

    发明人： Kenneth S. Collins ,  Chan-Lon Yang ,  Jerry Yuen-Kui Wong ,  Jeffrey Marks ,  Peter R. Keswick ,  David W. Groechel

    IPC分类号： C23C16/517 ,  H01L21/311 ,  C23F1/00

    CPC分类号： H01J37/32458 ,  C23C16/517 ,  H01J37/321 ,  H01J37/32165 ,  H01J37/32522 ,  H01J37/3266 ,  H01J37/32706 ,  H01L21/31116 ,  H01F2029/143

    摘要： A plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching oxygen-containing layers overlying non-oxygen-containing layers with high selectivity. Auxiliary RF bias energy applied to the wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. Various magnetic and voltage processing enhancement techniques are disclosed, along with other etch processes, deposition processes and combined etch/deposition processes. The disclosed invention provides processing of sensitive devices without damage and without microloading, thus providing increased yields. Etching of an oxygen-containing layer overlying a non-oxygen-containing layer can be achieved with high selectivity.

    摘要翻译： 等离子体反应室使用由RF能量（LF，MF或VHF）驱动的天线，其被感应耦合在反应堆穹顶内。 天线在室内产生高密度，低能量的等离子体，用于以高选择性蚀刻覆盖在非含氧层上的含氧层。 施加到晶片支撑阴极的辅助RF偏置能量控制阴极护套电压并且独立于密度来控制离子能量。 公开了各种磁和电压处理增强技术，以及其它蚀刻工艺，沉积工艺和组合蚀刻/沉积工艺。 所公开的发明提供敏感设备的处理而不损坏和不加载，从而提高产量。 可以以高选择性实现覆盖非含氧层的含氧层的蚀刻。

    VHF/UHF reactor system
    32.
    发明授权
    VHF/UHF reactor system 失效
    VHF / UHF反应堆系统

    公开(公告)号：US5210466A

    公开(公告)日：1993-05-11

    申请号：US852826

    申请日：1992-03-13

    申请人： Kenneth S. Collins ,  Craig A. Roderick ,  Chan-Lon Yang ,  David N. K. Wang ,  Dan Maydan

    发明人： Kenneth S. Collins ,  Craig A. Roderick ,  Chan-Lon Yang ,  David N. K. Wang ,  Dan Maydan

    IPC分类号： C23C16/509 ,  H01J37/32 ,  H05H1/46

    CPC分类号： H01J37/32174 ,  C23C16/509 ,  H01J37/32082 ,  H01J37/32091 ,  H05H1/46 ,  H05K2201/10015 ,  H05K2201/10689

    摘要： A plasma processing reactor is disclosed which incorporates an integral co-axial transmission line structure that effects low loss, very short transmission line coupling of ac power to the plasma chamber and therefore permits the effective use of VHF/UHF frequencies for generating a plasma. The use of VHF/UHF frequencies within the range 50-800 megahertz provides commercially viable processing rates (separate and simultaneous etching and deposition) and substantial reduction in sheath voltages compared to conventional frequencies such as 13.56 MHz. As a result, the probability of damaging electrically sensitive small geometry devices is reduced.

    摘要翻译： 公开了一种等离子体处理反应器，其包括整体的同轴传输线结构，其将低功率损耗，非常短的传输线耦合到等离子体室，因此允许有效地使用VHF / UHF频率来产生等离子体。 在常规频率（如13.56 MHz）下，VHF / UHF频率在50-800兆赫兹范围内的使用提供了商业上可行的处理速率（分离和同步蚀刻和沉积）和皮套电压的显着降低。 结果，减少了电敏感小型几何装置的损坏概率。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    36.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20120315734A1

    公开(公告)日：2012-12-13

    申请号：US13156345

    申请日：2011-06-09

    申请人： Chan-Lon Yang ,  Ger-Pin Lin ,  Tsuo-Wen Lu

    发明人： Chan-Lon Yang ,  Ger-Pin Lin ,  Tsuo-Wen Lu

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/265 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

    摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming an offset spacer on the sidewall of the gate structure; forming a cap layer to cover the substrate and the gate structure; performing an ion implantation process to implant carbon atoms into the cap layer; performing a first etching process to form a recess in the substrate adjacent to two sides of the gate structure; and forming an epitaxial layer in the recess.

    摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底，其中衬底包括其上的栅极结构; 在所述栅极结构的侧壁上形成偏移间隔物; 形成盖层以覆盖基板和栅极结构; 执行离子注入工艺以将碳原子注入到盖层中; 执行第一蚀刻工艺以在所述衬底中邻近所述栅极结构的两侧形成凹部; 以及在所述凹部中形成外延层。

    Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching
    40.
    发明授权
    Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching 失效
    通过原位聚合物沉积和蚀刻缩小掩模的等效效应临界尺寸

    公开(公告)号：US06368974B1

    公开(公告)日：2002-04-09

    申请号：US09365416

    申请日：1999-08-02

    申请人： Ming-Huan Tsai ,  Chan-Lon Yang

    发明人： Ming-Huan Tsai ,  Chan-Lon Yang

    IPC分类号： H01L21311

    CPC分类号： H01L21/31144

    摘要： A method for shrinking equivalent critical dimension of mask by in situ polymer deposition and etching is proposed. The invention comprises following key points: First, when a photo-resist is formed on a substrate by a mask and a photolithography process, a polymer layer is formed on said photo-resist. Second, a plasma reactor with at least two independent power sources is used to form and etch the polymer layer, where ion density and ion energy of plasma are adjusted respectively by different power sources. Third, voltages of all power sources are adjusted such that etching rate and depositing rate are equivalent on surface of the photo-resist and etching rate is obviously larger than depositing rate in bottom of any structure of the photo-resist. Therefore, the sidewall of any structure is filled by a conformal polymer layer and then width of any structure is efficiently decreased. By the way, the critical dimension of any structure is significant smaller than critical dimension of the mask. In other words, equivalent critical dimension of mask is shrunk by the invention. Obviously, the photo-resist with shrunk critical dimension can be used to form semiconductor device with critical dimension that is more narrow than critical dimension of the mask.

    摘要翻译： 提出了通过原位聚合物沉积和蚀刻收缩掩模的等效临界尺寸的方法。 本发明包括以下要点：首先，通过掩模和光刻工艺在基板上形成光致抗蚀剂时，在所述光致抗蚀剂上形成聚合物层。 其次，使用具有至少两个独立电源的等离子体反应器来形成和蚀刻聚合物层，其中等离子体的离子密度和离子能分别由不同的电源调节。 第三，调整所有电源的电压，使得蚀刻速率和沉积速率在光刻胶的表面上相当，并且蚀刻速率明显大于光刻胶的任何结构的底部的沉积速率。 因此，任何结构的侧壁由保形聚合物层填充，然后任何结构的宽度被有效地降低。 顺便说一句，任何结构的临界尺寸都明显小于掩模的临界尺寸。 换句话说，本发明缩小了掩模的等效临界尺寸。 显然，具有缩小的临界尺寸的光刻胶可用于形成临界尺寸比掩模的临界尺寸更窄的半导体器件。