公开(公告)号：US20120241739A1

公开(公告)日：2012-09-27

申请号：US13428008

申请日：2012-03-23

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/90 ,  H01L29/41733 ,  H01L29/785 ,  H01L29/78609

摘要： Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, a gate insulating film formed to cover the oxide semiconductor, and a strip-like gate which is formed to cover the gate insulating film and has a width of greater than or equal to 10 nm and less than or equal to 100 nm. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate, so that electrons injected from a source or a drain can be effectively removed, and most of the space between the source and the drain can be a depletion region; thus, off-state current can be reduced.

摘要翻译： 提供了一种具有小截止电流的场效应晶体管（FET），其用于小型化的半导体集成电路中。 场效应晶体管包括形成为基本上垂直于绝缘表面并且具有大于或等于1nm且小于或等于30nm的厚度的薄氧化物半导体，形成为覆盖氧化物半导体的栅极绝缘膜 以及形成为覆盖栅极绝缘膜并且具有大于或等于10nm且小于或等于100nm的宽度的条状栅极。 在这种结构中，薄氧化物半导体的三个表面被栅极覆盖，使得可以有效地去除从源极或漏极注入的电子，并且源极和漏极之间的大部分空间可以是耗尽区; 因此，可以减小截止电流。

公开(公告)号：US20120193759A1

公开(公告)日：2012-08-02

申请号：US13346172

申请日：2012-01-09

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： H01L29/02

CPC分类号： H01L28/91 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1207

摘要： A capacitor that has an electrode of an n-type semiconductor that is provided in contact with one surface of a dielectric, has a work function of 5.0 eV or higher, preferably 5.5 eV or higher, and includes nitrogen and at least one of indium, tin, and zinc. Since the electrode has a high work function, the dielectric can have a high potential barrier, and thus even when the dielectric is as thin as 10 nm or less, a sufficient insulating property can be maintained. In particular, a striking effect can be obtained when the dielectric is formed of a high-k material.

摘要翻译： 具有与电介质的一个表面接触的n型半导体的电极的电容器的功函数为5.0eV以上，优选为5.5eV以上，并且包括氮和铟， 锡和锌。 由于电极具有高的功函数，所以电介质可以具有高的势垒，因此即使当电介质薄到10nm以下时，也能够维持足够的绝缘性。 特别地，当电介质由高k材料形成时，可以获得显着的效果。

公开(公告)号：US20120182790A1

公开(公告)日：2012-07-19

申请号：US13344921

申请日：2012-01-06

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura

IPC分类号： G11C11/24

CPC分类号： H01L27/10808 ,  G11C5/10 ,  G11C11/401 ,  G11C11/4085 ,  H01L21/84 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10897 ,  H01L27/1207 ,  H01L28/91 ,  H01L29/7869

摘要： The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

摘要翻译： DRAM的存储器容量增强。 半导体存储器件包括：驱动器电路，其包括单晶半导体衬底的一部分，设置在驱动电路上的多层布线层;以及设置在多层布线层上的存储单元阵列层。 也就是说，存储单元阵列与驱动电路重叠。 因此，与在含有单晶体半导体材料的基板的同一平面上设置驱动电路和存储单元阵列的情况相比，可以提高半导体存储器件的集成度。

公开(公告)号：US08198683B2

公开(公告)日：2012-06-12

申请号：US12958739

申请日：2010-12-02

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L29/786

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US20120113345A1

公开(公告)日：2012-05-10

申请号：US13224395

申请日：2011-09-02

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Setsuo Nakajima ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Setsuo Nakajima ,  Yasuyuki Arai

IPC分类号： G02F1/136 ,  G02F1/1333

CPC分类号： G02F1/13452 ,  G02F1/1303 ,  G02F1/133305 ,  G02F1/1345 ,  G02F1/13454 ,  H01L21/67132 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01079

摘要： A driver circuit for use with a passive matrix or active matrix electro-optical display device such as a liquid crystal display is fabricated to occupy a reduced area. A circuit (stick crystal) having a length substantially equal to the length of one side of the matrix of the display device is used as the driver circuit. The circuit is bonded to one substrate of the display device, and then the terminals of the circuit are connected with the terminals of the display device. Subsequently, the substrate of the driver circuit is removed. The driver circuit can be formed on a large-area substrate such as a glass substrate, while the display device can be formed on a lightweight material having a high shock resistance such as a plastic substrate.

摘要翻译： 制造用于诸如液晶显示器的无源矩阵或有源矩阵电光显示装置的驱动电路以占据减小的面积。 使用具有与显示装置的矩阵的一侧的长度大致相等的长度的电路（棒状晶体）作为驱动电路。 电路接合到显示装置的一个基板，然后电路的端子与显示装置的端子连接。 随后，驱动电路的基板被去除。 驱动电路可以形成在诸如玻璃基板的大面积基板上，而显示装置可以形成在具有高抗震性的轻质材料如塑料基板上。

公开(公告)号：US20120075917A1

公开(公告)日：2012-03-29

申请号：US13236965

申请日：2011-09-20

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： G11C11/24

CPC分类号： H01L27/10897 ,  G11C7/02 ,  G11C8/14 ,  G11C11/404 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10805 ,  H01L27/10811 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255

摘要： In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m—1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.

摘要翻译： 在常规DRAM中，当电容器的电容减小时，容易发生读取数据的错误。 多个单元被连接到一个位线MBL_m。 每个单元包括子位线SBL_n_m和4至64个存储单元（存储单元CL_n_m-1等）。 此外，每个单元包括选择晶体管STr1_n_m和STr2_n_m，作为互补反相器等的放大器电路AMP_n_m连接到选择晶体管STr2_n_m。 由于子位线SBL_n_m的寄生电容足够小，所以每个存储单元的电容器中的电荷引起的电位变化都可以被放大器电路AMP_n_m放大而没有错误，并且可以被输出到位线。

公开(公告)号：US20110260158A1

公开(公告)日：2011-10-27

申请号：US13093018

申请日：2011-04-25

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： H01L27/105

CPC分类号： G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  G11C16/0433 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L28/40

摘要： To provide a semiconductor memory device storing data, in which a transistor whose leakage current between a source/drain in off state is small is used as a writing transistor. In a matrix of a memory unit formed of two memory cells, in each of which a drain of a writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor, a gate of the writing transistor, and the other electrode of the capacitor in a first memory cell are connected to a first word line, and a second word line, respectively. In a second memory cell, a gate of the writing transistor, and the other electrode of the capacitor are connected to the second word line, and the first word line, respectively. Further, to increase the degree of integration, gates of the reading transistors of memory cells are disposed in a staggered configuration.

摘要翻译： 为了提供一种存储数据的半导体存储器件，其中使用其中处于断开状态的源极/漏极之间的漏电流小的晶体管作为写入晶体管。 在由两个存储单元形成的存储器单元的矩阵中，每个写入晶体管的漏极连接到读取晶体管的栅极和电容器的一个电极，写入晶体管的栅极和另一个电极 第一存储单元中的电容器分别连接到第一字线和第二字线。 在第二存储单元中，写入晶体管的栅极和电容器的另一个电极分别连接到第二字线和第一字线。 此外，为了增加积分度，存储单元的读取晶体管的栅极以交错的配置布置。

公开(公告)号：US07968886B2

公开(公告)日：2011-06-28

申请号：US12361923

申请日：2009-01-29

申请人： Hideomi Suzawa ,  Yasuhiko Takemura

发明人： Hideomi Suzawa ,  Yasuhiko Takemura

IPC分类号： H01L21/00

CPC分类号： H01L29/78636 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  Y10S257/90

摘要： A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces of the gate electrodes and of the gate wiring. The presence of these substantially triangular side walls make milder the steps at which the second wiring goes over the gate wiring. This suppresses breakage of the second wiring.

摘要翻译： 一种半导体集成电路，包括薄膜晶体管，其中每个薄膜晶体管中的第二布线都被防止在台阶上断开。 在栅电极和从栅电极延伸的栅极布线上形成氮化硅膜。 在栅极电极和栅极布线的侧表面上形成由绝缘体构成的基本上三角形的区域。 这些基本上三角形的侧壁的存在使得第二布线越过栅极布线的步骤变得更加温和。 这抑制了第二布线的破损。

公开(公告)号：US07952097B2

公开(公告)日：2011-05-31

申请号：US09917633

申请日：2001-07-31

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang

IPC分类号： H01L29/04 ,  H01L31/036

CPC分类号： H01L29/66757 ,  H01L21/02532 ,  H01L21/02672 ,  H01L21/2022 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/04 ,  H01L29/78654 ,  H01L29/78675

摘要： A method for improving the reliability and yield of a thin film transistor by controlling the crystallinity thereof. The method comprises the steps of forming a gate electrode on an island amorphous silicon film, injecting an impurity using the gate electrode as a mask, forming a coating film containing at least one of nickel, iron, cobalt, platinum and palladium so that it adheres to parts of the impurity regions, and annealing it at a temperature lower than the crystallization temperature of pure amorphous silicon to advance the crystallization starting therefrom and to crystallize the impurity regions and channel forming region.

摘要翻译： 通过控制其结晶度来提高薄膜晶体管的可靠性和产率的方法。 该方法包括以下步骤：在岛状非晶硅膜上形成栅电极，使用栅电极作为掩模注入杂质，形成含有镍，铁，钴，铂和钯中的至少一种的涂膜，使其粘附 到部分杂质区域，并在低于纯非晶硅的结晶温度的温度下进行退火以促进从其开始的结晶，并使杂质区域和沟道形成区域结晶。

公开(公告)号：US07943930B2

公开(公告)日：2011-05-17

申请号：US12143035

申请日：2008-06-20

申请人： Hongyong Zhang ,  Toru Takayama ,  Yasuhiko Takemura ,  Akiharu Miyanaga ,  Hisashi Ohtani

发明人： Hongyong Zhang ,  Toru Takayama ,  Yasuhiko Takemura ,  Akiharu Miyanaga ,  Hisashi Ohtani

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  G09G2300/0408 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/1277 ,  H01L27/1296 ,  H01L29/66757

摘要： In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Neckel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650° C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.

摘要翻译： 在具有适于批量生产的结晶硅有源层的薄膜晶体管（TFT）中，通过离子注入或其它方式将催化元素引入到非晶硅膜的掺杂区域中。 该膜在低于玻璃基板的应变点的温度下结晶。 此外，形成栅极绝缘膜和栅电极。 杂质通过自对准过程引入。 然后，层压体在基板的应变点以下退火以活化掺杂剂杂质。 另一方面，Neckel或其它元素也用作促进非晶硅膜结晶的催化元素。 首先，将该催化元件与非晶硅膜的表面接触。 将膜在450至650℃加热以产生晶核。 将膜进一步在较高温度下加热以生长晶粒。 以这种方式，形成具有改善的结晶度的晶体硅膜。