公开(公告)号：US08564060B2

公开(公告)日：2013-10-22

申请号：US12834764

申请日：2010-07-12

申请人： Haruka Shimizu ,  Natsuki Yokoyama

发明人： Haruka Shimizu ,  Natsuki Yokoyama

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66734

摘要： There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.

摘要翻译： 制造含有具有大的沟道迁移率的UMOSFET的半导体功率器件并且其阈值电压可以降低而没有阻断电压的损失是没有有效的方法。 利用具有p体浓度低的狭窄区域和p体浓度高的宽区域的碳化硅沟槽MOSFET来提供具有大阻断电压的半导体器件。

公开(公告)号：US08524552B2

公开(公告)日：2013-09-03

申请号：US13363256

申请日：2012-01-31

申请人： Koichi Arai ,  Yasuaki Kagotoshi ,  Nobuo Machida ,  Natsuki Yokoyama ,  Haruka Shimizu

发明人： Koichi Arai ,  Yasuaki Kagotoshi ,  Nobuo Machida ,  Natsuki Yokoyama ,  Haruka Shimizu

IPC分类号： H01L21/337

CPC分类号： H01L29/36 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66909 ,  H01L29/8083

摘要： In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

摘要翻译： 通常，在诸如基于SiC的正常关断JFET的半导体有源元件中，其中杂质扩散速度显着低于硅中的杂质扩散速度，通过离子注入形成在源区中形成的沟槽的侧壁中形成栅极区。 然而，为了确保JFET的性能，需要高精度地控制栅极区域之间的面积。 此外，存在这样的问题，由于通过在源极区域中形成栅极区域而形成重掺杂的PN结，所以不能避免结电流的增加。 本发明提供一种常闭功率JFET及其制造方法，根据多次外延法形成栅极区域，该方法重复包括外延生长，离子注入和激活退火多次的工艺。

公开(公告)号：US08390001B2

公开(公告)日：2013-03-05

申请号：US13042528

申请日：2011-03-08

申请人： Haruka Shimizu ,  Natsuki Yokoyama

发明人： Haruka Shimizu ,  Natsuki Yokoyama

IPC分类号： H01L29/24

CPC分类号： H01L27/0629 ,  H01L21/8213 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1608 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/868 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

摘要： A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.

摘要翻译： 常闭型碳化硅结FET由于其特性的劣化而具有栅极不易使用的问题。 出现此问题的原因是为了实现常关，栅极电压应在0V关断，同时将导通状态栅极电压抑制在约2.5V，以防止电流通过pn 门和源之间的连接。 因此，从阈值电压到导通状态栅极电压的范围仅为约1V至2V，并且难以控制栅极电压。 在本发明中提供的是通过将常闭型碳化硅结FET的栅极耦合到具有等于或稍小于结FET的栅极电容的电容的元件而获得的电子电路器件。

公开(公告)号：US20120193641A1

公开(公告)日：2012-08-02

申请号：US13363256

申请日：2012-01-31

申请人： Koichi Arai ,  Yasuaki Kagotoshi ,  Nobuo Machida ,  Natsuki Yokoyama ,  Haruka Shimizu

发明人： Koichi Arai ,  Yasuaki Kagotoshi ,  Nobuo Machida ,  Natsuki Yokoyama ,  Haruka Shimizu

IPC分类号： H01L29/808 ,  H01L21/337

CPC分类号： H01L29/36 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66909 ,  H01L29/8083

摘要： In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

摘要翻译： 通常，在诸如基于SiC的正常关断JFET的半导体有源元件中，其中杂质扩散速度显着低于硅中的杂质扩散速度，通过离子注入形成在源区中形成的沟槽的侧壁中形成栅极区。 然而，为了确保JFET的性能，需要高精度地控制栅极区域之间的面积。 此外，存在这样的问题，由于通过在源极区域中形成栅极区域而形成重掺杂的PN结，所以不能避免结电流的增加。 本发明提供一种常闭功率JFET及其制造方法，根据多次外延法形成栅极区域，该方法重复包括外延生长，离子注入和激活退火多次的工艺。

公开(公告)号：US08203150B2

公开(公告)日：2012-06-19

申请号：US12453985

申请日：2009-05-28

申请人： Toshiyuki Ohno ,  Natsuki Yokoyama ,  Hajime Goto

发明人： Toshiyuki Ohno ,  Natsuki Yokoyama ,  Hajime Goto

IPC分类号： H01L29/24

CPC分类号： H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/0262

摘要： A buffer layer configured of the same conductive semiconductor layers of two or more layers as a drift layer is installed by epitaxial growth between a first semiconductor layer configuring the drift layer that is a layer in which components of the semiconductor device are made and a base substrate including a silicon carbide single crystal wafer. A step of donor concentration is provided at an interface between the drift layer and the buffer layer, an interface between the semiconductor layers configuring the buffer layer, and an interface between the buffer layer and the base substrate and the donor concentration of the drift layer side is lower than that of the base substrate side, thereby making it possible to convert most basal plane dislocations into threading edge dislocations as compared to the drift layer having one layer or the buffer layer configured of one layer.

摘要翻译： 由构成漂移层的构成半导体器件的部件的层的第一半导体层与基底基板之间的外延生长来安装由两层或多层作为漂移层的相同导电半导体层构成的缓冲层 包括碳化硅单晶晶片。 在漂移层和缓冲层之间的界面处设置供体浓度的步骤，构成缓冲层的半导体层之间的界面，缓冲层和基底基板之间的界面以及漂移层侧的供体浓度 低于基底侧，因此与具有一层或由一层构成的缓冲层的漂移层相比，可以将大多数基底面位错转换成穿线边缘位错。

公开(公告)号：US20110018004A1

公开(公告)日：2011-01-27

申请号：US12834764

申请日：2010-07-12

申请人： Haruka SHIMIZU ,  Natsuki Yokoyama

发明人： Haruka SHIMIZU ,  Natsuki Yokoyama

IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L21/336 ,  H01L29/201

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66734

摘要： There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.

摘要翻译： 制造含有具有大的沟道迁移率的UMOSFET的半导体功率器件并且其阈值电压可以降低而没有阻断电压的损失是没有有效的方法。 利用具有p体浓度低的狭窄区域和p体浓度高的宽区域的碳化硅沟槽MOSFET来提供具有大阻断电压的半导体器件。

公开(公告)号：US20090302328A1

公开(公告)日：2009-12-10

申请号：US12453985

申请日：2009-05-28

申请人： Toshiyuki Ohno ,  Natsuki Yokoyama ,  Hajime Goto

发明人： Toshiyuki Ohno ,  Natsuki Yokoyama ,  Hajime Goto

IPC分类号： H01L29/24 ,  H01L21/20

CPC分类号： H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/0262

摘要： A buffer layer configured of the same conductive semiconductor layers of two or more layers as a drift layer is installed by epitaxial growth between a first semiconductor layer configuring the drift layer that is a layer in which components of the semiconductor device are made and a base substrate including a silicon carbide single crystal wafer. A step of donor concentration is provided at an interface between the drift layer and the buffer layer, an interface between the semiconductor layers configuring the buffer layer, and an interface between the buffer layer and the base substrate and the donor concentration of the drift layer side is lower than that of the base substrate side, thereby making it possible to convert most basal plane dislocations into threading edge dislocations as compared to the drift layer having one layer or the buffer layer configured of one layer.

摘要翻译： 由构成漂移层的构成半导体器件的部件的层的第一半导体层与基底基板之间的外延生长来安装由两层或多层作为漂移层的相同导电半导体层构成的缓冲层 包括碳化硅单晶晶片。 在漂移层和缓冲层之间的界面处设置供体浓度的步骤，构成缓冲层的半导体层之间的界面，缓冲层和基底基板之间的界面以及漂移层侧的供体浓度 低于基底侧，因此与具有一层或由一层构成的缓冲层的漂移层相比，可以将大多数基底面位错转换成穿线边缘位错。

公开(公告)号：US07270012B2

公开(公告)日：2007-09-18

申请号：US11237897

申请日：2005-09-29

申请人： Natsuki Yokoyama ,  Shuntaro Machida ,  Yasushi Goto

发明人： Natsuki Yokoyama ,  Shuntaro Machida ,  Yasushi Goto

IPC分类号： G01L9/00

CPC分类号： G01L9/0073

摘要： The method for promoting the size reduction, the performance improvement and the reliability improvement of a semiconductor device embedded with pressure sensor is provided. In a semiconductor device embedded with pressure sensor, a part of an uppermost wiring is used as a lower electrode of a pressure detecting unit. A part of a silicon oxide film formed on the lower electrode is a cavity. On a tungsten silicide film formed on the silicon oxide film, a silicon nitride film is formed. The silicon nitride film has a function to fill a hole or holes and suppress immersion of moisture from outside to the semiconductor device embedded with pressure sensor. A laminated film of the silicon nitride film and the tungsten silicide film forms a diaphragm of the pressure sensor.

摘要翻译： 提供了一种用于促进嵌入压力传感器的半导体器件的尺寸减小，性能改进和可靠性改进的方法。 在嵌入压力传感器的半导体装置中，最上部布线的一部分用作压力检测单元的下部电极。 形成在下电极上的氧化硅膜的一部分是空腔。 在氧化硅膜上形成的硅化钨膜上形成氮化硅膜。 氮化硅膜具有填充孔或孔的功能，并且抑制水分从外部浸入到嵌入压力传感器的半导体器件中。 氮化硅膜和硅化钨膜的叠层膜形成压力传感器的膜片。

公开(公告)号：US07062344B2

公开(公告)日：2006-06-13

申请号：US10713012

申请日：2003-11-17

申请人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

发明人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC分类号： G06F19/00

CPC分类号： C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

摘要： Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system. Moreover, since the fabricating system including processing apparatuses is periodically controlled at a cycle time T min, the scheduling of a plurality of works can be made easy, to enhance the level of optimization, thus improving the productivity.

公开(公告)号：US07045843B2

公开(公告)日：2006-05-16

申请号：US10788369

申请日：2004-03-01

申请人： Yasushi Goto ,  Shuntaro Machida ,  Natsuki Yokoyama

发明人： Yasushi Goto ,  Shuntaro Machida ,  Natsuki Yokoyama

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01H59/0009 ,  H01H2001/0042 ,  H01H2001/0063

摘要： Disclosed herein is a latchable MEMS switch device capable of retaining its ON or OFF state even after the external power source is turned off. It is unnecessary not only to introduce novel materials such as magnetic material but also to form complicated structures. At least one of the cantilever and pull-down electrode of a cold switch is connected to a second MEMS switch. A capacitor between the cantilever and pull-down electrode of the cold switch is charged by the second MEMS switch. Thereafter since the cold switch is isolated in the device, the charge remains stored. Therefore, the cold switch can remain in the ON state since the charge continues to create electrostatic attraction between the cantilever and the pull-down electrode.

摘要翻译： 这里公开了即使在外部电源关闭之后也能够保持其接通或关断状态的可闭锁的MEMS开关装置。 不仅不需要引入诸如磁性材料的新型材料，而且形成复杂的结构。 冷开关的悬臂和下拉电极中的至少一个连接到第二MEMS开关。 冷开关的悬臂和下拉电极之间的电容器由第二MEMS开关充电。 此后，由于冷开关在器件中隔离，所以电荷保持存储。 因此，由于电荷继续在悬臂与下拉电极之间产生静电引力，所以冷开关可以保持在导通状态。