公开(公告)号：US20080144356A1

公开(公告)日：2008-06-19

申请号：US11945420

申请日：2007-11-27

申请人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

发明人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/79

摘要： There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and the corresponding bit line and an access element; selecting circuits selecting one of the plurality of resistive memory cells; and a filament-forming circuit supplying a filament-forming voltage to the selected resistive memory cell through the bit line coupled to the selected resistive memory cell while increasing the filament-forming voltage from a predetermined voltage level until filaments having a predetermined thickness are formed in the variable resistive material of the selected resistive memory cell.

摘要翻译： 提供了一种电阻式存储器件，该器件包括：多个字线和多个位线，其布置成使得字线与位线相交; 每个具有耦合在对应的字线和对应的位线之间的可变电阻材料的电阻性存储单元和一个存取元件; 选择所述多个电阻性存储单元之一的选择电路; 以及丝线形成电路，其通过耦合到所选择的电阻性存储单元的位线向所选择的电阻性存储单元提供丝状形成电压，同时从预定电压电平增加灯丝形成电压，直到形成具有预定厚度的灯丝 所选择的电阻性存储单元的可变电阻材料。

公开(公告)号：US20130051114A1

公开(公告)日：2013-02-28

申请号：US13562871

申请日：2012-07-31

申请人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

发明人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

IPC分类号： G11C5/14 ,  G11C11/00 ,  G11C11/16 ,  G11C11/22

CPC分类号： G11C13/0033 ,  G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0042 ,  G11C2013/0054

摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

摘要翻译： 包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。 感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号 第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。

公开(公告)号：US08116129B2

公开(公告)日：2012-02-14

申请号：US12872876

申请日：2010-08-31

申请人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  Y10S977/754

摘要： A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

摘要翻译： 一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个 分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字 形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线 形成在全局位线上，均匀分离，并沿第一方向延伸。

公开(公告)号：US07924639B2

公开(公告)日：2011-04-12

申请号：US12031115

申请日：2008-02-14

申请人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C13/0007 ,  G11C5/025 ,  G11C29/787 ,  G11C29/808 ,  G11C29/846 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

摘要： The present invention provides a nonvolatile memory device that uses a resistance material. The nonvolatile memory device includes: a stacked memory cell array having a plurality of memory cell layers stacked in a vertical direction, the stacked memory cell array having at least one memory cell group and at least one redundancy memory cell group; and a repair control circuit coupled to the stacked memory cell array, the repair control circuit configured to repair a defective one of the at least one memory cell group with a selected one of the at least one redundancy memory cell group. The features that enable repair improve the fabrication yield of the nonvolatile memory device.

摘要翻译： 本发明提供一种使用电阻材料的非易失性存储器件。 非易失性存储器件包括：堆叠存储单元阵列，具有沿垂直方向堆叠的多个存储单元层，所述堆叠存储单元阵列具有至少一个存储单元组和至少一个冗余存储单元组; 以及修复控制电路，其耦合到所述堆叠的存储单元阵列，所述修复控制电路被配置为用所述至少一个冗余存储器单元组中的所选择的一个来修复所述至少一个存储单元组中的有缺陷的一个。 能够修复的特征提高了非易失性存储器件的制造成品率。

公开(公告)号：US07920405B2

公开(公告)日：2011-04-05

申请号：US11957756

申请日：2007-12-17

申请人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

发明人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： G11C13/0064 ,  B82Y10/00 ,  G11C11/15 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

摘要： A non-volatile memory device includes a memory cell array including a memory cell array having word lines, bit lines, and non-volatile memory cells, each non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line. The variable resistive material has a resistance level that varies according to data to be stored. A selection circuit selects at least one non-volatile memory cell in which data will be written. An adaptive write circuit/method supplies a write bias to the selected non-volatile memory cell through the bit line connected to the selected non-volatile memory cell to write data in the selected non-volatile memory cell and varies (e.g., increases) the write bias until the resistance level of the selected non-volatile memory cell varies.

摘要翻译： 非易失性存储器件包括存储单元阵列，其包括具有字线，位线和非易失性存储器单元的存储单元阵列，每个非易失性存储单元具有可变电阻材料和连接在相应字之间的存取元件 线和相应的位线。 可变电阻材料具有根据要存储的数据而变化的电阻电平。 选择电路选择要写入数据的至少一个非易失性存储单元。 自适应写入电路/方法通过连接到所选择的非易失性存储器单元的位线向所选择的非易失性存储器单元提供写入偏置，以将数据写入所选择的非易失性存储单元中并且改变（例如，增加） 写入偏置，直到所选择的非易失性存储单元的电阻水平变化。

公开(公告)号：US07869256B2

公开(公告)日：2011-01-11

申请号：US11957812

申请日：2007-12-17

申请人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00 ,  G11C11/14

CPC分类号： G11C13/00 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/009

摘要： A non-volatile memory device is employed in which data values are determined by the polarities at both ends of a cell, The non-volatile memory device includes a first decoder which decodes a plurality of predetermined bit values of a row address into a first address and is disposed in a row direction of a memory cell array; a second decoder which decodes the other bit values of the row address into a second address and is disposed in a column direction of the memory cell array; and a driver which applies bias voltages to a word line which corresponds to the first address or the second address in accordance with the data values. By including first and second decoders and decoding a row address in two steps, a bi-directional RRAM according to the present invention can perform addressing at high speeds while reducing chip size.

摘要翻译： 使用非易失性存储器件，其中数据值由单元两端的极性确定。非易失性存储器件包括将行地址的多个预定位值解码为第一地址的第一解码器 并且设置在存储单元阵列的行方向上; 第二解码器，其将所述行地址的其他位值解码为第二地址，并且被布置在所述存储单元阵列的列方向上; 以及根据数据值对与第一地址或第二地址对应的字线施加偏置电压的驱动器。 通过包括第一和第二解码器并以两个步骤对行地址进行解码，根据本发明的双向RRAM可以在降低芯片尺寸的同时以高速执行寻址。

公开(公告)号：US20100320433A1

公开(公告)日：2010-12-23

申请号：US12872876

申请日：2010-08-31

申请人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： G11C5/063 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  Y10S977/754

摘要： A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

摘要翻译： 一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个 分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字 形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线 形成在全局位线上，均匀分离，并沿第一方向延伸。

公开(公告)号：US07586776B2

公开(公告)日：2009-09-08

申请号：US11945420

申请日：2007-11-27

申请人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

发明人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/79

摘要： There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and the corresponding bit line and an access element; selecting circuits selecting one of the plurality of resistive memory cells; and a filament-forming circuit supplying a filament-forming voltage to the selected resistive memory cell through the bit line coupled to the selected resistive memory cell while increasing the filament-forming voltage from a predetermined voltage level until filaments having a predetermined thickness are formed in the variable resistive material of the selected resistive memory cell.

摘要翻译： 提供了一种电阻式存储器件，该器件包括：多个字线和多个位线，其布置成使得字线与位线相交; 每个具有耦合在对应的字线和对应的位线之间的可变电阻材料的电阻性存储单元和一个存取元件; 选择所述多个电阻性存储单元之一的选择电路; 以及丝线形成电路，其通过耦合到所选择的电阻性存储单元的位线向所选择的电阻性存储单元提供丝状形成电压，同时从预定电压电平增加灯丝形成电压，直到形成具有预定厚度的灯丝 所选择的电阻性存储单元的可变电阻材料。

公开(公告)号：US20080089105A1

公开(公告)日：2008-04-17

申请号：US11865491

申请日：2007-10-01

申请人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C5/06 ,  H01L21/82

CPC分类号： G11C5/063 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  Y10S977/754

摘要： A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

摘要翻译： 一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个 分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字 形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线 形成在全局位线上，均匀分离，并沿第一方向延伸。

公开(公告)号：US09042152B2

公开(公告)日：2015-05-26

申请号：US13562871

申请日：2012-07-31

申请人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

发明人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C11/56

CPC分类号： G11C13/0033 ,  G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0042 ,  G11C2013/0054

摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

摘要翻译： 包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。 感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号 第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。