公开(公告)号：US20230411348A1

公开(公告)日：2023-12-21

申请号：US17842093

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Bernd Waidhas ,  Thomas Wagner

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/29 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/0652 ,  H01L24/73 ,  H01L24/16 ,  H01L24/08 ,  H01L24/09 ,  H01L21/565 ,  H01L21/486 ,  H01L23/293 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/481 ,  H01L24/05 ,  H01L2924/37001 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/381 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L24/13 ,  H01L2224/13147 ,  H01L23/49816

Abstract: Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die having first bond-pads on a first surface; an organic dielectric material in contact with the first surface; second bond-pads on a second surface of the organic dielectric material opposite to the first surface; through-dielectric vias (TDVs) in the dielectric material between the first bond-pads and the second bond-pads, wherein the TDVs are in direct contact with the first bond-pads and the second bond-pads; a second IC die embedded in the organic dielectric material and coupled to the first bond-pads by first interconnects; and a package substrate coupled to the second bond-pads by second interconnects.

公开(公告)号：US20230299032A1

公开(公告)日：2023-09-21

申请号：US17699209

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Jan Proschwitz ,  Stefan Reif ,  Vishnu Prasad

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13016 ,  H01L2224/13076 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2924/013 ,  H01L2924/014

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a die having a first conductive contact on a surface; a substrate having a second conductive contact on a surface; and an interconnect electrically coupling the first conductive contact of the die and the second conductive contact of the substrate, wherein the interconnect includes a portion of a nanowire on the second conductive contact and an intermetallic compound (IMC) surrounding at least a portion of the nanowire on the second conductive contact.

公开(公告)号：US20230299014A1

公开(公告)日：2023-09-21

申请号：US17698430

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Abdallah Bacha ,  Bernd Waidhas ,  Eduardo De Mesa ,  Carlton Hanna ,  Mohan Prashanth Javare Gowda

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/73 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate, including a core and a stiffener in the core, wherein the stiffener is along a perimeter of the core; and a die electrically coupled to the substrate.

公开(公告)号：US20230299013A1

公开(公告)日：2023-09-21

申请号：US17698365

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Abdallah Bacha ,  Bernd Waidhas ,  Eduardo De Mesa ,  Carlton Hanna ,  Mohan Prashanth Javare Gowda

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/32 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; and a microelectronic subassembly electrically coupled to the substrate by interconnects, the microelectronic subassembly including an interposer having a surface; a first die electrically coupled to the surface of the interposer; a second die electrically coupled to the surface of the interposer; and a stiffener ring coupled to the surface of the interposer along the perimeter of the interposer.

公开(公告)号：US20230282615A1

公开(公告)日：2023-09-07

申请号：US17685871

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Thomas Wagner ,  Abdallah Bacha ,  Vishnu Prasad ,  Mohan Prashanth Javare Gowda ,  Bernd Waidhas ,  Sonja Koller ,  Eduardo De Mesa ,  Jan Proschwitz ,  Lizabeth Keser

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

公开(公告)号：US20230197599A1

公开(公告)日：2023-06-22

申请号：US17554112

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Harald Gossner ,  Wolfgang Molzer ,  Georg Seidemann ,  Michael Langenbuch ,  Martin Ostermayr ,  Joachim Singer ,  Thomas Wagner ,  Klaus Herold

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.

公开(公告)号：US20220415806A1

公开(公告)日：2022-12-29

申请号：US17355747

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/50

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.

公开(公告)号：US20220415805A1

公开(公告)日：2022-12-29

申请号：US17355726

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/50 ,  H01L23/522 ,  H01L23/36

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a second microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a redistribution layer on the insulating material including a second conductive pathway electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and a wire bond electrically coupling the first and the second conductive pathways.

公开(公告)号：US12243828B2

公开(公告)日：2025-03-04

申请号：US17355770

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

公开(公告)号：US20240405433A1

公开(公告)日：2024-12-05

申请号：US18328107

申请日：2023-06-02

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georg Seidemann ,  Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Tae Young Yang

IPC: H01Q9/04 ,  H01Q1/22

Abstract: Disclosed herein are antenna modules, electronic assemblies, and communication devices. An example antenna module includes an IC component, an antenna patch support over a face of the IC component, and a stack of antenna patches vertically arranged at least partially above one another, where a first antenna patch of the stack is an antenna patch closest to the IC component, and a second antenna patch of the stack is an antenna patch closest to the first antenna patch. The first antenna patch is on the face of the IC component while the second and further antenna patches of the stack are on or in the antenna patch support and are electrically isolated from all electrically conductive material pathways in the antenna patch support and in the IC component.