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    System, Apparatus And Method For Loose Lock-Step Redundancy Power Management
    31.
    发明申请
    System, Apparatus And Method For Loose Lock-Step Redundancy Power Management 审中-公开

    公开(公告)号：US20200057480A1

    公开(公告)日：2020-02-20

    申请号：US16663645

    申请日：2019-10-25

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

    IPC: G06F1/324 ,  G06F1/3296

    Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

    Method and apparatus to control current transients in a processor
    33.
    发明授权
    Method and apparatus to control current transients in a processor 有权
    控制处理器中电流瞬变的方法和装置

    公开(公告)号：US09411395B2

    公开(公告)日：2016-08-09

    申请号：US13865463

    申请日：2013-04-18

    Applicant: Intel Corporation

    Inventor： Nir Rosenzweig ,  Zeev Sperber ,  Efraim Rotem

    IPC: G06F1/32 ,  G06F1/26

    CPC classification number: G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D10/172

    Abstract: In an embodiment, a processor includes at least one core. The at least one core includes an execution unit and a current protection (IccP) controller. The IccP controller may receive instruction width information associated with one or more instructions of an instruction queue prior to execution of the instructions by the execution unit. The IccP controller may determine an anticipated highest current level (Icc) for the at least one core based on the instruction width information. The IccP controller may generate a request for a first license for the at least one core that is associated with the Icc. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括至少一个核。 至少一个核心包括执行单元和电流保护（IccP）控制器。 IccP控制器可以在由执行单元执行指令之前接收与指令队列的一个或多个指令相关联的指令宽度信息。 IccP控制器可以基于指令宽度信息确定至少一个核心的预期最高电流电平（Icc）。 IccP控制器可以产生对于与Icc相关联的至少一个核心的第一许可证的请求。 描述和要求保护其他实施例。

    Method and apparatus to protect a processor against excessive power usage
    34.
    发明授权
    Method and apparatus to protect a processor against excessive power usage 有权
    防止处理器过度使用电力的方法和装置

    公开(公告)号：US09292362B2

    公开(公告)日：2016-03-22

    申请号：US13926089

    申请日：2013-06-25

    Applicant: Intel Corporation

    Inventor： Lev Makovsky ,  Zeev Sperber ,  Efraim Rotem ,  Nir Rosenzweig ,  Stanislav Shwartsman ,  Raanan Sade ,  Igor Yanover ,  Gavri Berger ,  Tomer Weiner ,  Ron Gabor

    IPC: G06F1/04 ,  G06F9/54 ,  G06F9/30 ,  G06F9/48 ,  G06F1/32

    CPC classification number: G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

    Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

    Providing Lifetime Statistical Information For A Processor
    35.
    发明申请
    Providing Lifetime Statistical Information For A Processor 有权
    为处理器提供终身统计信息

    公开(公告)号：US20160070321A1

    公开(公告)日：2016-03-10

    申请号：US14482148

    申请日：2014-09-10

    Applicant: Intel Corporation

    Inventor： Dorit Shapira ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Esfir Natanzon ,  Nir Rosenzweig

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

    Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括多个核和耦合到核的功率控制单元（PCU）。 PCU具有应力检测器，用于接收处理器运行的电压和温度，并计算包括有效可靠性压力在内的寿命统计信息，在诸如个人计算机，服务器计算机等计算系统的多个引导周期之后维持寿命统计信息， 平板电脑，智能电话或任何其他计算平台，基于生存期统计信息来控制处理器的一个或多个操作参数，并且经由接口将至少一部分生命周期统计信息传达给用户和/或管理实体 的处理器。 描述和要求保护其他实施例。

    BALANCED CONTROL OF PROCESSOR TEMPERATURE
    36.
    发明申请
    BALANCED CONTROL OF PROCESSOR TEMPERATURE 有权
    加工温度平衡控制

    公开(公告)号：US20160048181A1

    公开(公告)日：2016-02-18

    申请号：US14461039

    申请日：2014-08-15

    Applicant: Intel Corporation

    Inventor： Nir Rosenzweig ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman ,  Tomer Ziv

    IPC: G06F1/20 ,  G06F1/32 ,  G01K13/00

    CPC classification number: G06F1/206 ,  G01K1/026 ,  G01K13/00 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324

    Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括多个核心和多个温度传感器，其中每个核心靠近至少一个温度传感器。 该处理器还包括一个功率控制单元（PCU），其包括用于接收包括来自每个温度传感器的相应温度值的温度数据的温度逻辑。 响应于温度数据的最高温度值超过阈值的指示，温度逻辑是根据基于多个核心中的至少两个的指令执行特性的确定的策略来调整多个域频率。 每个域频率与包括多个核心中的至少一个核心的对应域相关联，并且每个域频率是可独立调整的。 描述和要求保护其他实施例。

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