中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

57 records (took 0.014 seconds)

    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate
    31.
    发明申请
    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 失效
    在半导体基板上筛选多个样品的组合处理方法

    公开(公告)号：US20130138380A1

    公开(公告)日：2013-05-30

    申请号：US13731715

    申请日：2012-12-31

    Applicant: INTERMOLECULAR, INC.

    Inventor： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

    IPC: G01R31/28

    CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

    Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

    Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

    Blocking Layers for Leakage Current Reduction in DRAM Devices
    32.
    发明申请
    Blocking Layers for Leakage Current Reduction in DRAM Devices 有权
    阻止DRAM器件泄漏电流降低的层

    公开(公告)号：US20130113079A1

    公开(公告)日：2013-05-09

    申请号：US13658065

    申请日：2012-10-23

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L29/92

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

    Formation of a Masking Layer on a Dielectric Region to Facilitate Formation of a Capping Layer on Electrically Conductive Regions Separated by the Dielectric Region
    34.
    发明申请
    Formation of a Masking Layer on a Dielectric Region to Facilitate Formation of a Capping Layer on Electrically Conductive Regions Separated by the Dielectric Region 审中-公开
    在介电区域上形成掩模层，以便在由介电区域分离的导电区域上形成覆盖层

    公开(公告)号：US20150179500A1

    公开(公告)日：2015-06-25

    申请号：US14625488

    申请日：2015-02-18

    Applicant: Intermolecular, Inc.

    Inventor： Thomas R. Boussie ,  David E. Lazovsky ,  Sandra G. Malhotra

    IPC: H01L21/768 ,  H01L21/288 ,  H01L21/02 ,  H01L21/31

    CPC classification number: H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

    Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料 在电介质区域。 可以选择性地在导电区域或非选择性地形成覆盖层; 在任一种情况下，形成在电介质区域上的覆盖层材料随后可以被去除，从而确保覆盖层材料仅在导电区域上形成。 硅烷类材料可用于形成掩模层。 覆盖层可以由导电材料，半导体材料或绝缘材料形成，并且可以使用包括常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积的任何适当的工艺形成。

    Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
    35.
    发明授权
    Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region 有权
    在电介质区域上形成掩模层，以便在由电介质区域分隔的导电区域上形成覆盖层

    公开(公告)号：US08975180B2

    公开(公告)日：2015-03-10

    申请号：US14257694

    申请日：2014-04-21

    Applicant: Intermolecular, Inc.

    Inventor： Thomas R. Boussie ,  David E. Lazovsky ,  Sandra G. Malhotra

    IPC: H01L21/44 ,  H01L21/768 ,  B82Y30/00

    CPC classification number: H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

    Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料 在电介质区域。 可以选择性地在导电区域或非选择性地形成覆盖层; 在任一种情况下，形成在电介质区域上的覆盖层材料随后可以被去除，从而确保覆盖层材料仅在导电区域上形成。 硅烷类材料可用于形成掩模层。 覆盖层可以由导电材料，半导体材料或绝缘材料形成，并且可以使用包括常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积的任何适当的工艺形成。

    Methods for Reproducible Flash Layer Deposition
    36.
    发明申请
    Methods for Reproducible Flash Layer Deposition 有权
    可再生闪蒸层沉积的方法

    公开(公告)号：US20140187018A1

    公开(公告)日：2014-07-03

    申请号：US13731452

    申请日：2012-12-31

    Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC.

    Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L49/02

    CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

    Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

    Abstract translation: 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。

    High Work Function, Manufacturable Top Electrode
    38.
    发明申请
    High Work Function, Manufacturable Top Electrode 有权
    高功能，可制造顶电极

    公开(公告)号：US20140183697A1

    公开(公告)日：2014-07-03

    申请号：US13737263

    申请日：2013-01-09

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

    IPC: H01L29/92

    CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

    Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

    Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
    39.
    发明授权
    Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region 有权
    在电介质区域上形成掩模层，以便在由电介质区域分隔的导电区域上形成覆盖层

    公开(公告)号：US08709943B2

    公开(公告)日：2014-04-29

    申请号：US13892516

    申请日：2013-05-13

    Applicant: Intermolecular, Inc.

    Inventor： Thomas R. Boussie ,  David E. Lazovsky ,  Sandra G. Malhotra

    IPC: H01L21/44

    CPC classification number: H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

    Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料 在电介质区域。 可以选择性地在导电区域或非选择性地形成覆盖层; 在任一种情况下，形成在电介质区域上的覆盖层材料随后可以被去除，从而确保覆盖层材料仅在导电区域上形成。 硅烷类材料可用于形成掩模层。 覆盖层可以由导电材料，半导体材料或绝缘材料形成，并且可以使用包括常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积的任何适当的工艺形成。

Patent Agency Ranking