公开(公告)号：US09515141B1

公开(公告)日：2016-12-06

申请号：US15135844

申请日：2016-04-22

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L29/66795 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin.

公开(公告)号：US20160351448A1

公开(公告)日：2016-12-01

申请号：US15086440

申请日：2016-03-31

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung H. Chen ,  Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L21/768

CPC classification number: F24S30/452 ,  E04B1/34357 ,  E04B1/346 ,  E04B7/163 ,  F24S20/61 ,  F24S2030/18 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  Y02A30/22 ,  Y02B10/20 ,  Y02E10/47

Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

公开(公告)号：US09508713B2

公开(公告)日：2016-11-29

申请号：US14198005

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/16 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L27/0886 ,  H01L21/3085 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

Abstract translation: 一种形成鳍状场效应晶体管器件的方法包括在衬底上形成包括硅的一个或多个第一鳍片，在一个或多个第一鳍片的侧面上形成外延层，以及去除一个或多个第一鳍片以形成 多个第二鳍片。

公开(公告)号：US20160322501A1

公开(公告)日：2016-11-03

申请号：US14699491

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li

IPC: H01L29/78 ,  H01L21/322 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/322 ,  H01L21/3221 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

Abstract translation: 在硅片的侧壁表面上形成硅锗合金。 采用氧化工艺或热退火将硅片的一部分转换成硅锗合金翅片。 在一些实施例中，硅锗合金翅片具有宽的上部和较窄的下部。 在这样的实施例中，宽的上部具有比较窄的下部更大的锗含量。 在其他实施例中，硅锗合金翅片具有窄的上部和较宽的下部。 在本实施例中，硅锗合金翅片的较窄上部具有比硅锗合金翅片的较宽下部更大的锗含量。

公开(公告)号：US20160247883A1

公开(公告)日：2016-08-25

申请号：US15078024

申请日：2016-03-23

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L29/161 ,  H01L29/78

CPC classification number: H01L21/02636 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/02639 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/785

Abstract: A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.

Abstract translation: 形成半导体翅片的方法包括从第一半导体材料形成多个牺牲模板翅片; 在牺牲模板翅片的暴露的侧壁表面上外延生长第二半导体材料的翅片; 以及去除所述多个牺牲模板翅片。

公开(公告)号：US20160233243A1

公开(公告)日：2016-08-11

申请号：US15082199

申请日：2016-03-28

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device with dual isolation are described. The CMOS device includes an n-type field effect transistor (nFET) region, the nFET region including one or more fins comprised of strained silicon, the one or fins in the nFET region being formed on an insulator. The CMOS device also includes a p-type field effect transistor (pFET) region, the pFET region including one or more fins comprised of silicon (Si) or silicon germanium (SiGe) on epitaxially grown silicon and including a shallow trench isolation (STI) fill to isolate the one or more fins of the pFET region from each other.

公开(公告)号：US20160233241A1

公开(公告)日：2016-08-11

申请号：US14618442

申请日：2015-02-10

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L21/027 ,  H01L21/3105 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device with dual isolation are described. The CMOS device includes an n-type field effect transistor (nFET) region, the nFET region including one or more fins comprised of strained silicon, the one or fins in the nFET region being formed on an insulator. The CMOS device also includes a p-type field effect transistor (pFET) region, the pFET region including one or more fins comprised of silicon (Si) or silicon germanium (SiGe) on epitaxially grown silicon and including a shallow trench isolation (STI) fill to isolate the one or more fins of the pFET region from each other.

Abstract translation: 一种在包括p型场效应晶体管器件（pFET）和n型场效应晶体管（nFET）器件的双隔离互补金属氧化物半导体（CMOS）器件中形成鳍片的方法和具有 描述了双重隔离。 CMOS器件包括n型场效应晶体管（nFET）区域，nFET区域包括由应变硅组成的一个或多个鳍片，nFET区域中的一个或鳍形成在绝缘体上。 CMOS器件还包括p型场效应晶体管（pFET）区域，pFET区域包括在外延生长的硅上包括硅（Si）或硅锗（SiGe）的一个或多个鳍，并且包括浅沟槽隔离（STI） 填充以将pFET区域中的一个或多个翅片彼此隔离。

公开(公告)号：US20160233240A1

公开(公告)日：2016-08-11

申请号：US14618397

申请日：2015-02-10

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L21/027 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/0276 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849

Abstract: A method of forming fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device are described. The method includes forming a strained silicon-on-insulator (SSOI) layer in both a pFET region and an nFET region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pFET region to expose the bulk substrate, epitaxially growing silicon (Si) from the bulk substrate in only the pFET region, and epitaxially growing additional semiconductor material on the Si in only the pFET region. The method also includes forming fins from the additional semiconductor material and a portion of the Si grown on the bulk substrate in the pFET region, and forming fins from the strained silicon layer and the insulator in the nFET region.

公开(公告)号：US20160225770A1

公开(公告)日：2016-08-04

申请号：US15082161

申请日：2016-03-28

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/10 ,  H01L27/12

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming replacement fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor device (nFET) and a CMOS device are described. The method includes forming strained silicon (Si) fins from a strained silicon-on-insulator (SSOI) layer in both an nFET region and a pFET region, forming insulating layers over the strained Si fins, and forming trenches within the insulating layers to expose the strained Si fins in the pFET region only. The method also includes etching the strained Si fins in the pFET region to expose a buried oxide (BOX) layer of the SSOI layer, etching the exposed portions of the BOX layer to expose a bulk substrate, epitaxially growing a Si portion of pFET replacement fins from the bulk substrate, and epitaxially growing silicon germanium (SiGe) portions of the pFET replacement fins on the Si portion of the pFET replacement fins.

Abstract translation: 描述了在包括p型场效应晶体管器件（pFET）和n型场效应晶体管器件（nFET）和CMOS器件的互补金属氧化物半导体（CMOS）器件中形成替换鳍片的方法 。 该方法包括从nFET区域和pFET区域中的应变绝缘体上硅（SSOI）层形成应变硅（Si）鳍，在应变Si散热片上形成绝缘层，并在绝缘层内形成沟槽以暴露 仅在pFET区域中的应变Si散热片。 该方法还包括蚀刻pFET区域中的应变Si散热片以暴露SSOI层的掩埋氧化物（BOX）层，蚀刻BOX层的暴露部分以暴露大块衬底，外延生长pFET替代鳍片的Si部分 并且在pFET替换鳍片的Si部分上外延生长pFET替换鳍片的硅锗（SiGe）部分。

公开(公告)号：US20160111525A1

公开(公告)日：2016-04-21

申请号：US14976867

申请日：2015-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/306 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.