公开(公告)号：US09313921B2

公开(公告)日：2016-04-12

申请号：US14015063

申请日：2013-08-30

Applicant: International Business Machines Corporation

Inventor： Thomas J. Brunschwiler ,  Evan G. Colgan ,  John U. Knickerbocker ,  Bruno Michael ,  Chin Lee Ong ,  Cornelia K. Tsang

IPC: H05K7/20 ,  H01L23/367 ,  H01L23/427 ,  H01L25/065 ,  H01L29/06 ,  H01L23/498

CPC classification number: H05K7/20381 ,  H01L23/367 ,  H01L23/427 ,  H01L23/49816 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/81141 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06593 ,  H05K7/20309 ,  H05K7/20327

Abstract: A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.

Abstract translation: 用于实现两相冷却的封装结构包括设置在基板上的芯片堆叠和封装芯片堆叠的封装盖。 芯片堆叠包括多个联合芯片，通过芯片堆叠的中心区域形成的中心入口歧管和外围出口歧管。 中央输入歧管包括入口喷嘴，用于将液体冷却剂供入形成在相邻联结芯片之间的流动空腔中。 外围出口歧管从流动腔输出加热的液体和蒸气。 包装盖包括与中心入口歧管对准的中心冷却剂供给入口和外围液体蒸气出口，以输出从外围出口歧管排出的加热的液体和蒸气。 引导壁可以包括在流动腔中以引导液体和蒸气的流动，并且引导壁可以被布置成形成由中央入口歧管的不同入口喷嘴供给的径向流动通道。

公开(公告)号：US20150035173A1

公开(公告)日：2015-02-05

申请号：US14226953

申请日：2014-03-27

Applicant: International Business Machines Corporation

Inventor： Bing Dang ,  John U. Knickerbocker ,  Eric Peter Lewandowski ,  Cornelia Kang-I Tsang

IPC: H01L23/00 ,  H01L21/66 ,  C09J179/08 ,  B32B37/12 ,  H01L21/02

CPC classification number: B23K26/36 ,  G01R31/2607 ,  H01L21/302 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T156/1158 ,  Y10T156/1917 ,  Y10T428/265 ,  Y10T428/30 ,  Y10T428/31678

Abstract: Methods are provided to form adhesive materials that are used to temporarily bond handler wafers to device wafers, and which enable mid-wavelength infrared laser ablation release techniques to release handler wafers from device wafers.

Abstract translation: 提供了用于形成用于将处理器晶片暂时地接合到器件晶片的粘合剂材料的方法，并且使得能够使中波长红外激光烧蚀释放技术从器件晶片释放处理器晶片。

公开(公告)号：US20140147986A1

公开(公告)日：2014-05-29

申请号：US13746359

申请日：2013-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bing Dang ,  John U. Knickerbocker ,  Cornelia Kang-I Tsang

IPC: H01L21/02

CPC classification number: H01L21/02002 ,  B82Y30/00 ,  H01L21/67092 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10S977/902 ,  Y10T156/1158 ,  Y10T156/1917 ,  Y10T428/24355 ,  Y10T428/265 ,  Y10T428/31678

Abstract: Methods are provided for handling a device wafer. For example, a method includes providing a stack structure having a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and handler wafer, and irradiating the bonding structure with long-wavelength infrared energy to ablate the bonding structure.

Abstract translation: 提供了处理器件晶片的方法。 例如，一种方法包括提供具有器件晶片，处理器晶片和布置在器件晶片和处理器晶片之间的接合结构的堆叠结构，并且用长波长红外能量照射接合结构以消融接合结构。

公开(公告)号：US20140106473A1

公开(公告)日：2014-04-17

申请号：US13649458

申请日：2012-10-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： PAUL S. ANDRY ,  Russell A. Budd ,  John U. Knickerbocker ,  Robert E. Trzcinski ,  Douglas C. La Tulipe, JR.

IPC: H01L21/02

CPC classification number: H01L23/49827 ,  H01L21/02 ,  H01L21/2007 ,  H01L21/6835 ,  H01L29/00 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a semiconductor wafer and the transparent handler having the release layer applied thereon. The semiconductor wafer is bonded to the transparent handler using the adhesive layer. The semiconductor wafer is processed while it is bonded to the transparent handler. The release layer is ablated by irradiating the release layer through the transparent handler with a laser. The semiconductor wafer is removed from the transparent handler.

公开(公告)号：US11362382B2

公开(公告)日：2022-06-14

申请号：US15416564

申请日：2017-01-26

Applicant: International Business Machines Corporation

Inventor： Paul S. Andry ,  Bing Dang ,  John U. Knickerbocker ,  Yang Liu ,  Jae-Woong Nah ,  Adinath Narasgond ,  Bucknell C. Webb

IPC: H01M50/10 ,  H01M50/209 ,  H01M6/40 ,  H01M10/04

Abstract: A micro-battery is provided in which a metallic sealing layer is used to provide a hermetic seal between an anode side of the micro-battery and the cathode side of the micro-battery. In accordance with the present application, the metallic sealing layer is formed around a perimeter of each metallic anode structure located on the anode side and then the metallic sealing layer is bonded to a solderable metal layer of a wall structure present on the cathode side. The wall structure contains a cavity that exposes a metallic current collector structure, the cavity is filled with battery materials.

公开(公告)号：US10940265B2

公开(公告)日：2021-03-09

申请号：US16435517

申请日：2019-06-09

Applicant: International Business Machines Corporation

Inventor： Bing Dang ,  John U. Knickerbocker ,  Joana S. B. T. Maria ,  Bucknell C. Webb ,  Steven L. Wright

IPC: A61M5/168 ,  A61M5/142 ,  A61M5/44 ,  A61M5/172

Abstract: A digital biomedical device includes a substrate forming a reservoir, a membrane comprising a first layer and a second layer having a strain therebetween, the membrane sealing the reservoir, and a controller configured to activate the membrane and release at least a portion of the strain causing the membrane curl and open the reservoir.

公开(公告)号：US10687425B2

公开(公告)日：2020-06-16

申请号：US15821446

申请日：2017-11-22

Applicant: International Business Machines Corporation

Inventor： Paul S. Andry ,  Qianwen Chen ,  Bing Dang ,  John U. Knickerbocker ,  Minhua Lu ,  Robert J. Polastre ,  Bucknell C. Webb

IPC: H05K3/30 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K1/11 ,  H05K1/03 ,  H05K1/02 ,  G01R31/44 ,  G01R31/309 ,  G01R31/28 ,  H05K13/00

Abstract: An electro-optical module assembly is provided that includes a flexible substrate having a first surface and a second surface opposite the first surface, wherein the flexible substrate contains an opening located therein that extends from the first surface to the second surface. An optical component is located on the second surface of the flexible substrate and is positioned to have a surface exposed by the opening. At least one electronic component is located on a first portion of the first surface of the flexible substrate, and at least one micro-energy source is located on a second portion of the first surface of the flexible substrate.

公开(公告)号：US20200098638A1

公开(公告)日：2020-03-26

申请号：US16693526

申请日：2019-11-25

Applicant: International Business Machines Corporation

Inventor： Bing Dang ,  Jeffrey D. Gelorme ,  John U. Knickerbocker

IPC: H01L21/78 ,  H01L23/31 ,  H01L23/29 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56

Abstract: A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

公开(公告)号：US10522383B2

公开(公告)日：2019-12-31

申请号：US14668534

申请日：2015-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bing Dang ,  Jeffrey D. Gelorme ,  John U. Knickerbocker

IPC: H01L21/683 ,  C08L63/00 ,  C08G59/06 ,  C09J163/00 ,  C09J171/00 ,  C08K3/04 ,  C09J9/00

Abstract: A bonding material including a phenoxy resin thermoplastic component, and a carbon black filler component. The carbon black filler component is present in an amount greater than 1 wt. %. The carbon black filler converts the phenoxy resin thermoplastic component from a material that transmits infra-red (IR) wavelengths to a material that absorbs a substantial portion of infra-red (IR) wavelengths.

公开(公告)号：US20190311082A1

公开(公告)日：2019-10-10

申请号：US16433675

申请日：2019-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Li-Wen Hung ,  Wanki Kim ,  John U. Knickerbocker ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC: G06F17/50 ,  H01L25/07 ,  G06F15/78 ,  H01L25/11 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/683

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.