公开(公告)号：US20180068892A1

公开(公告)日：2018-03-08

申请号：US15802285

申请日：2017-11-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L23/482 ,  H01L21/74 ,  H01L21/683

Abstract: A device structure with a backside contact includes a silicon-on-insulator substrate including a device layer, a buried insulator layer, and an electrically-conducting connection in a trench. A final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

公开(公告)号：US09786835B2

公开(公告)日：2017-10-10

申请号：US14712092

申请日：2015-05-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H01L41/293 ,  H01L21/768 ,  H01L23/48 ,  H03H9/64 ,  G06F17/50 ,  H01L23/00 ,  H01L41/08 ,  H01L41/25 ,  H01L27/06 ,  H01L49/02 ,  H01L23/66 ,  H01L25/16

CPC classification number: H01L41/293 ,  G06F17/5063 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L25/16 ,  H01L27/0694 ,  H01L28/40 ,  H01L41/0815 ,  H01L41/25 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2225/06548 ,  H03H9/64

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

公开(公告)号：US09740080B2

公开(公告)日：2017-08-22

申请号：US14927621

申请日：2015-10-30

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G02F1/295 ,  G02F1/313 ,  G02F1/01 ,  G02F1/025

CPC classification number: G02F1/3137 ,  G02F1/0147 ,  G02F1/025 ,  G02F2201/58 ,  G02F2203/15

Abstract: Various particular embodiments include an optical structure, including: a photonic microring including an integral signal detector for detecting a level of an optical signal in the photonic microring; and a controller, coupled to the signal detector, for selectively adjusting a resonant frequency of the photonic microring based on the detected level of the optical signal in the photonic microring.

公开(公告)号：US20160308270A1

公开(公告)日：2016-10-20

申请号：US14687002

申请日：2015-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hanyi Ding ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01Q1/22 ,  H01L21/762

CPC classification number: H01Q1/2283 ,  H01L21/76224 ,  H01L23/5227 ,  H01Q9/16

Abstract: Approaches for an on-chip antenna are provided. A method includes forming an antenna in an insulator layer at a front side of a substrate. The method also includes forming a trench in the substrate underneath the antenna. The method further includes forming a fill material in the trench. The substrate is composed of a material having a first dielectric constant. The fill material has a second dielectric constant that is less than the first dielectric constant.

Abstract translation: 提供了片上天线的方法。 一种方法包括在基板的正面的绝缘体层中形成天线。 该方法还包括在天线下方的衬底中形成沟槽。 该方法还包括在沟槽中形成填充材料。 基板由具有第一介电常数的材料构成。 填充材料具有小于第一介电常数的第二介电常数。

公开(公告)号：US09455187B1

公开(公告)日：2016-09-27

申请号：US14742958

申请日：2015-06-18

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/30 ,  H01L21/768 ,  H01L21/762 ,  H01L21/683

CPC classification number: H01L23/528 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/1203 ,  H01L29/0649 ,  H01L2221/68327 ,  H01L2221/68372

Abstract: Methods for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. A trench is formed that extends through the device layer or a trench isolation region in the device layer and that further extends partially through the buried insulator layer. A sacrificial material is deposited in the trench and, thereafter, at least one dielectric layer is formed on the device layer. An opening is formed in the at least one dielectric layer that communicates with the trench. After the opening is formed, the sacrificial material is removed from the trench with access through the opening. After the sacrificial material is removed from the trench, the trench is filled with a contact plug and the opening is filled with a contact coupled with the contact plug.

Abstract translation: 使用包括器件层，埋入绝缘体层和处理晶片的绝缘体上硅衬底制造背面器件接触的方法。 形成沟槽，其延伸穿过器件层中的器件层或沟槽隔离区域，并进一步延伸穿过掩埋绝缘体层。 牺牲材料沉积在沟槽中，此后在器件层上形成至少一个电介质层。 在与沟槽连通的至少一个电介质层中形成开口。 在形成开口之后，通过开口进入牺牲材料从沟槽移除。 在牺牲材料从沟槽移除之后，沟槽填充有接触塞，并且开口填充有与接触插塞相连的触点。

公开(公告)号：US09349793B2

公开(公告)日：2016-05-24

申请号：US14480215

申请日：2014-09-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/306 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/764 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Abstract translation: 公开了具有下面的气隙的场效应晶体管（FET）和制造方法。 该方法包括在衬底的预定深度处形成非晶层。 该方法还包括在非晶层下方的衬底中形成气隙。 该方法还包括在非晶层和气隙之上的衬底的有源区中形成完全隔离的晶体管。

公开(公告)号：US20150243879A1

公开(公告)日：2015-08-27

申请号：US14712092

申请日：2015-05-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H01L41/293 ,  G06F17/50 ,  H01L23/00 ,  H01L41/08 ,  H01L41/25

CPC classification number: H01L41/293 ,  G06F17/5063 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L25/16 ,  H01L27/0694 ,  H01L28/40 ,  H01L41/0815 ,  H01L41/25 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2225/06548 ,  H03H9/64

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract translation: 在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

公开(公告)号：US08796057B2

公开(公告)日：2014-08-05

申请号：US13766952

申请日：2013-02-14

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Mark D. Jaffe

IPC: H01L21/00

CPC classification number: H01L27/14603 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14689

Abstract: Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.

Abstract translation: 像素传感器单元，例如CMOS光学成像器，制造和设计结构的方法被提供有防止载流子漂移到扩散区域的隔离结构。 像素传感器单元包括感光区域和与感光区域相邻的栅极。 像素传感器单元还包括与栅极相邻的扩散区域。 像素传感器单元还包括位于栅极的沟道区域周围和感光区域下方的隔离区域，其防止在光敏区域中收集的电子漂移到扩散区域。

公开(公告)号：US08689152B2

公开(公告)日：2014-04-01

申请号：US13783438

申请日：2013-03-04

Applicant: International Business Machines Corporation

Inventor： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Paul D. Kartschoke ,  Stephen E. Luce ,  Anthony K. Stamper

IPC: G06F17/50 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L21/30 ,  H01L21/46

CPC classification number: G06F17/5077 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/481 ,  H01L23/535 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/045 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01007 ,  H01L2924/01022 ,  H01L2924/00

Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract translation: 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除后侧硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US10964840B2

公开(公告)日：2021-03-30

申请号：US16552664

申请日：2019-08-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson

IPC: H01L31/18 ,  H01L31/103 ,  H01L31/028 ,  H01L31/0232 ,  G02B6/12 ,  H01P1/17 ,  H01L31/02 ,  H01P3/16

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.