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31.发明授权公开(公告)号：US10658493B2
公开(公告)日：2020-05-19
申请号：US16515759
申请日：2019-07-18
发明人： Zhenxing Bi , Kangguo Cheng , Nicolas J. Loubet , Xin Miao , Wenyu Xu , Chen Zhang
摘要： Embodiments of the invention are directed to a nano sheet field effect transistor (FET) device that includes a gate spacer and an inner spacer. The gate spacer includes an upper segment and a lower segment. The inner spacer has a first selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The lower segment has the first selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The upper segment has a second selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The first etch selectivity is greater than the second etch selectivity.
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公开(公告)号：US10580858B2
公开(公告)日：2020-03-03
申请号：US16103070
申请日：2018-08-14
IPC分类号： H01L29/06 , H01L29/786 , H01L29/66 , H01L29/423 , H01L29/775 , B82Y10/00 , H01L21/308 , H01L29/10 , H01L21/28 , H01L27/092 , H01L21/8238
摘要： Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having equal thickness work function metal layers. A nanosheet stack is formed on a substrate. The nanosheet stack includes a first sacrificial layer formed on a first nanosheet. A hard mask is formed on the first sacrificial layer and the first sacrificial layer is removed to form a cavity between the hard mask and the first nanosheet. A work function layer is formed to fill the cavity between the hard mask and the first nanosheet.
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公开(公告)号：US20200035824A1
公开(公告)日：2020-01-30
申请号：US16592455
申请日：2019-10-03
发明人： Huimei Zhou , Su Chen Fan , Shogo Mochizuki , Peng Xu , Nicolas J. Loubet
IPC分类号： H01L29/78 , H01L27/06 , H01L29/08 , H01L29/66 , H01L27/092
摘要： A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.
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34.发明申请公开(公告)号：US20190378906A1
公开(公告)日：2019-12-12
申请号：US16006173
申请日：2018-06-12
IPC分类号： H01L29/423 , H01L29/66 , H01L21/311 , H01L21/28
摘要： A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.
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公开(公告)号：US20190252495A1
公开(公告)日：2019-08-15
申请号：US16395557
申请日：2019-04-26
发明人： Ruqiang Bao , Michael A. Guillorn , Terence B. Hook , Nicolas J. Loubet , Robert R. Robison , Reinaldo A. Vega , Tenko Yamashita
IPC分类号： H01L29/06 , B82Y10/00 , H01L29/423 , H01L21/8234 , H01L29/66 , H01L29/786 , H01L29/10 , H01L29/08
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/823412 , H01L27/088 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/786
摘要： Semiconductor devices and methods of making the same include forming a stack of alternating layers of channel material and sacrificial material. The sacrificial material is etched away to free the layers of channel material. A gate stack is formed around the layers of channel material. At least one layer of channel material is deactivated. Source and drain regions are formed in contact with the at least one layer of active channel material.
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公开(公告)号：US10249739B2
公开(公告)日：2019-04-02
申请号：US15446636
申请日：2017-03-01
发明人： Michael A. Guillorn , Terence B. Hook , Nicolas J. Loubet , Robert R. Robison , Reinaldo A. Vega
IPC分类号： H01L21/02 , H01L29/786 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/423 , H01L29/165
摘要： A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer, patterning the heteroepitaxial film stack, forming a dummy gate stack with sidewall spacers, and forming a cladded or embedded epitaxial source/drain material along the patterned heteroepitaxial film stack sidewalls. The method further includes removing the dummy gate stack, partially removing the at least one sacrificial layer, and forming a replacement gate stack.
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公开(公告)号：US10170552B2
公开(公告)日：2019-01-01
申请号：US15626734
申请日：2017-06-19
IPC分类号： H01L27/12 , H01L29/06 , H01L21/02 , H01L21/306 , H01L29/423 , H01L29/66 , H01L21/3213 , H01L21/84 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/10 , H01L29/161
摘要： Nanosheet semiconductor devices and methods of forming the same include forming a first stack in a first device region, the first stack including layers of a first channel material and layers of a sacrificial material. A second stack is formed in a second device region, the second stack including layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner. The liner protects the second channel material from the wet etch.
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公开(公告)号：US20180374761A1
公开(公告)日：2018-12-27
申请号：US16023687
申请日：2018-06-29
IPC分类号： H01L21/8238 , H01L29/06 , H01L29/786 , H01L21/02 , H01L27/092 , H01L29/423
摘要： Embodiments of the invention are directed to a method of forming an insulation region during fabrication of a nanosheet channel field effect transistor (FET). The method includes forming a first sacrificial nanosheet across from a major surface of a substrate, wherein the first sacrificial nanosheet includes a first semiconductor material at a concentration percentage less than or equal to about fifty percent. A first nanosheet stack is formed on an opposite side of the first sacrificial nanosheet from the major surface of the substrate, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial stack nanosheets, wherein a thickness dimension of the first sacrificial nanosheet is greater than a thickness dimension of at least one of the alternating channel nanosheets. An oxidation operation is performed that converts the first sacrificial nanosheet to a dielectric oxide, wherein the insulation region includes the dielectric oxide.
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公开(公告)号：US10043748B1
公开(公告)日：2018-08-07
申请号：US15810940
申请日：2017-11-13
IPC分类号： H01L29/00 , H01L29/06 , H01L23/525 , H01L21/268 , H01L23/532 , H01L21/306 , H01L21/265 , H01L29/66 , H01L27/06 , H01L27/12 , H01L29/49 , H01L29/786
摘要： Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.
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公开(公告)号：US09972684B2
公开(公告)日：2018-05-15
申请号：US15453118
申请日：2017-03-08
CPC分类号： H01L29/1079 , H01L21/02381 , H01L21/02439 , H01L21/0245 , H01L21/02483 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/0259 , H01L21/0262 , H01L29/0684 , H01L29/16 , H01L29/7849
摘要： A method for forming a compressively strained semiconductor substrate includes forming a lattice adjustment layer on a semiconductor substrate by forming compound clusters within an epitaxially grown semiconductor matrix. The lattice adjustment layer includes a different lattice constant than the semiconductor substrate. A rare earth oxide is grown and lattice matched to the lattice adjustment layer. A semiconductor layer is grown and lattice matched to the rare earth oxide and includes a same material as the semiconductor substrate such that the semiconductor layer is compressively strained.
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