公开(公告)号：US20130134517A1

公开(公告)日：2013-05-30

申请号：US13732806

申请日：2013-01-02

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Balasubramanian S. Haran ,  David V. Horak

IPC: H01L29/786

CPC classification number: H01L29/0653 ,  H01L21/76283 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/78609

Abstract: After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

公开(公告)号：US12237325B2

公开(公告)日：2025-02-25

申请号：US17136860

申请日：2020-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Su Chen Fan ,  Shogo Mochizuki ,  Peng Xu ,  Nicolas J. Loubet

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H10B41/20 ,  H10B43/20 ,  H10B53/20 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/417

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

公开(公告)号：US20240178292A1

公开(公告)日：2024-05-30

申请号：US17994487

申请日：2022-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Indira Seshadri ,  Su Chen Fan ,  Jay William Strane ,  Stuart Sieg ,  Shogo Mochizuki

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/775

Abstract: A semiconductor structure is presented including semiconductor layers of a first nanosheet stack, semiconductor layers of a second nanosheet stack formed over and having a stepped nanosheet formation with respect to the semiconductor layers of the first nanosheet stack, a first epitaxial growth formed adjacent the semiconductor layers of the first nanosheet stack, and a second epitaxial growth formed adjacent the semiconductor layers of the second nanosheet stack such that the second epitaxial growth has a stepped formation with respect to the first epitaxial growth. The second epitaxial growth has a volume greater than a volume of the first epitaxial growth.

公开(公告)号：US20240014211A1

公开(公告)日：2024-01-11

申请号：US18471718

申请日：2023-09-21

Applicant: International Business Machines Corporation

Inventor： Tsung-Sheng Kang ,  Ardasheir Rahman ,  Tao Li ,  Su Chen Fan

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H03K19/20 ,  H01L29/78 ,  H03K19/173 ,  H01L27/06

CPC classification number: H01L27/092 ,  H01L21/823885 ,  H01L29/66666 ,  H03K19/20 ,  H01L29/7827 ,  H03K19/173 ,  H01L27/0688 ,  H01L21/823871 ,  H01L29/42376

Abstract: A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.

公开(公告)号：US20230411397A1

公开(公告)日：2023-12-21

申请号：US17807158

申请日：2022-06-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Su Chen Fan ,  Ravikumar Ramachandran ,  Oleg Gluschenkov

IPC: H01L27/12 ,  H01L23/522 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L23/5226 ,  H01L21/84

Abstract: A microelectronic structure including a stacked transistor having a lower transistor and an upper transistor. A shared contact in contact with a lower source/drain of the first lower transistor and an upper source/drain of the upper transistor. The shared contact includes a silicide layer, a metal plug layer, and a conductive metal layer.

公开(公告)号：US11817502B2

公开(公告)日：2023-11-14

申请号：US17569133

申请日：2022-01-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Su Chen Fan ,  Shogo Mochizuki ,  Peng Xu ,  Nicolas J. Loubet

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/06 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L27/0688 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66795

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

公开(公告)号：US20230282748A1

公开(公告)日：2023-09-07

申请号：US17653476

申请日：2022-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shogo Mochizuki ,  Su Chen Fan ,  Nicolas Jean Loubet ,  Xuan Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/28568 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor structure includes a plurality of nanosheet (NS) channel layers having a plurality of source/drain (S/D) regions on sidewalls thereof; and a continuous contact via being in direct contact with the plurality of S/D regions, wherein the continuous contact via has a substantially same horizontal distance to each of the plurality of NS channel layers. A method of manufacturing the same is also provided.

公开(公告)号：US20230268388A1

公开(公告)日：2023-08-24

申请号：US17651919

申请日：2022-02-22

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Su Chen Fan ,  Julien Frougier ,  Maruf Amin Bhuiyan ,  Pouya Hashemi ,  Takashi Ando ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L27/088 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/0649 ,  H01L29/66742

Abstract: Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top active region. The width of the top of the top active region is smaller than the width of bottom of the top active region. The stacked FET further comprises a top contact in direct contact with a top surface of the top active region. The stacked FET further comprises a bottom active region located substantially below the top active region. The stacked FET further comprises a bottom contact in direct contact with a top surface of the bottom active region. The bottom contact is wider at a top end than at a bottom end.

公开(公告)号：US20230187442A1

公开(公告)日：2023-06-15

申请号：US17551950

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Christopher J. Waskiewicz ,  Yann Mignot ,  Jeffrey C. Shearer ,  Hemanth Jagannathan

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823418

Abstract: A semiconductor device comprises a substrate including at least one vertical fin extending from the substrate, a bottom source/drain region beneath the at least one vertical fin, a top source/drain region disposed above the at least one vertical fin, a metal gate structure, a contact coupled to the top source/drain region and first and second contact spacers disposed on each side of the contact.

公开(公告)号：US20230170395A1

公开(公告)日：2023-06-01

申请号：US17537638

申请日：2021-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  Su Chen Fan

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L29/401 ,  H01L21/76895 ,  H01L29/42392

Abstract: A semiconductor device is presented that includes source/drain epitaxial regions disposed over a substrate, source/drain contacts (CA) disposed in direct contact with the source/drain epitaxial regions, where at least one of the CA contacts directly contacts a buried power rail or backside power rail through a via-to-BPR (VBPR) contact, a dielectric cap disposed over one or more of the CA contacts, and a local interconnect constructed in direct contact with one area of the dielectric cap such that a portion of the local interconnect is vertically aligned with the backside power rail. A backside power distribution network (BSPDN) is disposed adjacent the backside power rail.