公开(公告)号：US08470706B2

公开(公告)日：2013-06-25

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US08383483B2

公开(公告)日：2013-02-26

申请号：US12541562

申请日：2009-08-14

申请人： John C. Arnold ,  Glenn A. Biery ,  Alessandro C. Callegari ,  Tze-Chiang Chen ,  Michael P. Chudzik ,  Bruce B. Doris ,  Michael A. Gribelyuk ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Joseph S. Newbury ,  Vamsi K. Paruchuri ,  Michelle L. Steen

发明人： John C. Arnold ,  Glenn A. Biery ,  Alessandro C. Callegari ,  Tze-Chiang Chen ,  Michael P. Chudzik ,  Bruce B. Doris ,  Michael A. Gribelyuk ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Joseph S. Newbury ,  Vamsi K. Paruchuri ,  Michelle L. Steen

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.

摘要翻译： 本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。 第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的 门导体。 第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。 可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

公开(公告)号：US08129843B2

公开(公告)日：2012-03-06

申请号：US12853354

申请日：2010-08-10

申请人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

发明人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/5329 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

摘要： Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.

摘要翻译： 在形成双镶嵌金属互连结构的超低k电介质材料中的等离子体损伤通过在管线沟槽的侧壁上设置保护隔离物来减少。 致密沟槽底部区域可以直接附加地形成在线沟槽的暴露的水平表面下方。 保护间隔物和/或致密的沟槽底部区域在用于去除在双镶嵌金属互连结构中使用的一次性通孔填充塞的等离子体条带过程中保护超低k金属间介电层免受等离子体损伤。

公开(公告)号：US20080203447A1

公开(公告)日：2008-08-28

申请号：US11678338

申请日：2007-02-23

申请人： John C. Arnold ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： John C. Arnold ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L29/76 ,  H01L21/31

CPC分类号： H01L21/32139 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/32105 ,  H01L21/3211 ,  H01L21/32136 ,  H01L29/4966 ,  Y10S257/90

摘要： A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps.

摘要翻译： 提供了一种栅极电极结构，其从底部到顶部包括任选的，但优选的金属层，富含Ge的层和富含Si的层。 富含Ge的层的侧壁包括表面钝化层。 本发明的栅极电极结构用作MOSFET的低温电激活栅电极，其中其材料及其制造方法与现有的MOSFET制造技术相兼容。 本发明的栅电极结构在低处理温度（小于750℃的数量级）下被电激活。 此外，本发明的栅电极结构还使栅极耗尽效应最小化，不会污染标准MOS制造设备，并且具有足够低的暴露表面的反应性，使得这种栅电极结构与常规MOSFET处理步骤相容。

公开(公告)号：US20070285513A1

公开(公告)日：2007-12-13

申请号：US11451992

申请日：2006-06-13

申请人： John C. Arnold

发明人： John C. Arnold

IPC分类号： H04N7/18

CPC分类号： G07G1/0018

摘要： An emulator of the type suitable to simulate connection of an intended device to another device in the absence of an actual connection therebetween. The emulator may be configured to simulate any number of connections, such as but not limited to printer port, display port, and scale port connection. The emulator may be used with any number of elements, such as but not limited to point of sale (POS) device. The emulator may be configured to receive data from the port, and optionally, to transmit the received data to remote locations, such as through network communications.

摘要翻译： 适用于在没有实际连接的情况下模拟预期设备与另一设备的连接的仿真器。 模拟器可以被配置为模拟任何数量的连接，例如但不限于打印机端口，显示端口和标度端口连接。 仿真器可以与任何数量的元件一起使用，例如但不限于销售点（POS）设备。 仿真器可以被配置为从端口接收数据，并且可选地，例如通过网络通信将接收的数据发送到远程位置。

公开(公告)号：US08536630B2

公开(公告)日：2013-09-17

申请号：US13301274

申请日：2011-11-21

申请人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

发明人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

IPC分类号： H01L29/772

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

摘要翻译： 在一个实施例中，制造晶体管器件的方法包括：提供半导体形貌，其包括设置在一对电介质间隔物之间​​的半导体衬底之上的栅极导体; 各向异性地蚀刻介电间隔物的相对侧上的半导体衬底的暴露区域，以在衬底中形成凹陷区域; 在所述凹陷区域中氧化所述衬底的暴露表面以在其上形成氧化物; 从凹陷区域的底部除去氧化物，同时将氧化物保持在凹陷区域的侧壁上; 并且各向同性蚀刻所述基板，使得所述凹陷区域切割所述一对电介质间隔物。

公开(公告)号：US20090072401A1

公开(公告)日：2009-03-19

申请号：US11857805

申请日：2007-09-19

申请人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

发明人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

摘要： Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.

摘要翻译： 在形成双镶嵌金属互连结构的超低k电介质材料中的等离子体损伤通过在管线沟槽的侧壁上设置保护隔离物来减少。 致密沟槽底部区域可以直接附加地形成在线沟槽的暴露的水平表面下方。 保护间隔物和/或致密的沟槽底部区域在用于去除在双镶嵌金属互连结构中使用的一次性通孔填充塞的等离子体条带过程中保护超低k金属间介电层免受等离子体损伤。

公开(公告)号：US20120329269A1

公开(公告)日：2012-12-27

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US20120061684A1

公开(公告)日：2012-03-15

申请号：US13301274

申请日：2011-11-21

申请人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

发明人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

IPC分类号： H01L29/772

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

摘要翻译： 在一个实施例中，制造晶体管器件的方法包括：提供半导体形貌，其包括设置在一对电介质间隔物之间​​的半导体衬底之上的栅极导体; 各向异性地蚀刻介电间隔物的相对侧上的半导体衬底的暴露区域，以在衬底中形成凹陷区域; 在所述凹陷区域中氧化所述衬底的暴露表面以在其上形成氧化物; 从凹陷区域的底部除去氧化物，同时将氧化物保持在凹陷区域的侧壁上; 并且各向同性蚀刻所述基板，使得所述凹陷区域切割所述一对电介质间隔物。

公开(公告)号：US07880241B2

公开(公告)日：2011-02-01

申请号：US11678338

申请日：2007-02-23

申请人： John C. Arnold ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： John C. Arnold ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L21/02

CPC分类号： H01L21/32139 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/32105 ,  H01L21/3211 ,  H01L21/32136 ,  H01L29/4966 ,  Y10S257/90

摘要： A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps.

摘要翻译： 提供了一种栅极电极结构，其从底部到顶部包括任选的，但优选的金属层，富含Ge的层和富含Si的层。 富含Ge的层的侧壁包括表面钝化层。 本发明的栅极电极结构用作MOSFET的低温电激活栅电极，其中其材料及其制造方法与现有的MOSFET制造技术相兼容。 本发明的栅电极结构在低处理温度（小于750℃的数量级）下被电激活。 此外，本发明的栅电极结构还使栅极耗尽效应最小化，不会污染标准MOS制造设备，并且具有足够低的暴露表面的反应性，使得这种栅电极结构与常规MOSFET处理步骤相容。