公开(公告)号：US06815737B2

公开(公告)日：2004-11-09

申请号：US10799819

申请日：2004-03-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L2710

CPC分类号： H01L21/76897 ,  H01L21/76888 ,  H01L21/76895

摘要： A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.

公开(公告)号：US06358813B1

公开(公告)日：2002-03-19

申请号：US09713766

申请日：2000-11-15

申请人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

发明人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

IPC分类号： H01L2120

CPC分类号： H01L28/92

摘要： Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

摘要翻译： 描述了通过在半导体介质上提供第一固态电极图案来增加半导体电容器的电容的方法，以有效增加所述第一电极图案的表面积的方式蚀刻所述第一电极图案上的地形特征， 所述电极图案上的电介质层基本上符合所述形貌特征，并且在所述电介质层上沉积第二固态电极图案，并且与所述第一固态电极图案充分绝缘，从而产生具有所述第一固态的电容 电极图案。

公开(公告)号：US06313492B1

公开(公告)日：2001-11-06

申请号：US09110487

申请日：1998-07-06

申请人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

发明人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

IPC分类号： H01L27108

CPC分类号： H01L28/82 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/0274 ,  H01L21/3085

摘要： A photoresist composition is disclosed having both negative tone and positive tone responses, giving rise to spaces being formed in the areas of diffraction which are exposed to intermediate amounts of radiation energy. This resist material may be used to print doughnut shapes or may be subjected to a second masking step, to print lines. Additionally, larger and smaller features may be obtained using a gray-scale filter in the reticle, to create larger areas of intermediate exposure areas.

摘要翻译： 公开了具有负色调和正色调响应的光致抗蚀剂组合物，在曝光到中等辐射能量的衍射区域中形成空间。 该抗蚀剂材料可以用于印刷圆环形状或者可以进行第二掩蔽步骤以打印线。 另外，可以使用掩模版中的灰度滤光片获得更大和更小的特征，以产生更大面积的中间曝光区域。

公开(公告)号：US06277543B1

公开(公告)日：2001-08-21

申请号：US09369412

申请日：1999-08-05

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： G03C500

CPC分类号： G03F7/70466 ,  G03F7/038 ,  G03F7/2022 ,  H01L21/0274

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the “loops” formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.

摘要翻译： 本发明的优选实施例通过提供使用混合抗蚀剂形成不连接特征的方法来克服现有技术的局限性。 该方法使用修剪工艺来修剪由混合抗蚀剂形成的“环”的连接特征。 这允许该方法形成多个未链接的特征而不是循环。 为了修剪端部，通过第二曝光步骤或通过利用灰度光罩，形成与窄特征线相邻的相对较大的修整区域。 更宽或更宽的开放区域允许在窄特征线中形成特征并且从相对较大的区域修剪特征，从而导致区域特征而不是环。

公开(公告)号：US06271555B1

公开(公告)日：2001-08-07

申请号：US09052403

申请日：1998-03-31

申请人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Wendell P. Noble, Jr.

发明人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Wendell P. Noble, Jr.

IPC分类号： H01L27108

CPC分类号： H01L27/10873 ,  H01L27/10891 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S257/908

摘要： A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.

摘要翻译： 公开了一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。 栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。 晶体管还具有具有源/漏区的单晶半导体衬底。 主动导电字线沉积在分段栅极导体的顶部并与其电接触，该字线是具有顶部和侧壁的导电材料。 电绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。 围绕有源字线的绝缘材料包括覆盖顶部并且围绕其侧壁的一部分的氮化硅，并且二氧化硅围绕有源字线的侧壁的其余部分。 位线触点接触源极/漏极区域和围绕有源字线的绝缘材料，从而使位线接触到字线。 还提供了完全封装的通过字线，其与分段栅极导体和有源字线间隔开并与之隔绝。

公开(公告)号：US06207493B1

公开(公告)日：2001-03-27

申请号：US09136586

申请日：1998-08-19

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/743 ,  H01L27/10876

摘要： The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

公开(公告)号：US6114725A

公开(公告)日：2000-09-05

申请号：US93928

申请日：1998-06-09

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

IPC分类号： H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

公开(公告)号：US6100172A

公开(公告)日：2000-08-08

申请号：US182173

申请日：1998-10-29

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/768 ,  H01L21/822 ,  H01L29/78 ,  H01L21/22 ,  H01L21/425 ,  H01L21/8234

CPC分类号： H01L29/66613 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76895 ,  H01L21/822 ,  H01L29/7835

摘要： The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

摘要翻译： 本发明提供一种用于在水平表面上形成自对准间隔物的方法，同时从垂直表面移除间隔物材料。 优选的方法使用可以通过使用植入物使其不溶于显影剂的抗蚀剂。 通过在具有垂直和水平表面的基底上保形地沉积抗蚀剂，植入抗蚀剂并显影抗蚀剂，在保持在水平表面上的同时将抗蚀剂从垂直表面上除去。 因此，当从垂直表面移除间隔物材料时，在水平表面上形成自对准间隔物。 然后可以将该水平表面间隔件用于进一步制造。 优选的方法可以用于许多不同的工艺，其中存在需要对衬底的垂直和水平表面进行差异化处理。

公开(公告)号：US08803321B2

公开(公告)日：2014-08-12

申请号：US13490542

申请日：2012-06-07

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/535 ,  H01L21/283

CPC分类号： H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

摘要翻译： 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 此后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的电介质材料的选择性蚀刻去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制的通孔腔，并沿着宽度方向 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

公开(公告)号：US20130207270A1

公开(公告)日：2013-08-15

申请号：US13371493

申请日：2012-02-13

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L23/49

CPC分类号： H01L23/485 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5283 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

摘要翻译： 形成半导体结构的方法，包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物，所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷，使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽，以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。