公开(公告)号：US20070205459A1

公开(公告)日：2007-09-06

申请号：US11653359

申请日：2007-01-16

Applicant: Eun-Suk Cho ,  Dong-Gun Park ,  Choong-Ho Lee ,  Jong-Jin Lee ,  Jeong-Dong Choe

Inventor： Eun-Suk Cho ,  Dong-Gun Park ,  Choong-Ho Lee ,  Jong-Jin Lee ,  Jeong-Dong Choe

IPC: H01L29/788

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7854 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory device includes a semiconductor pin including a first semiconductor pattern, a second semiconductor pattern on the first semiconductor pattern, and a third semiconductor pattern, disposed between the first semiconductor pattern and the second semiconductor pattern, connecting the first semiconductor pattern and the second semiconductor pattern, a charge storage layer on the second semiconductor pattern with a tunneling insulation layer interposed therebetween, and a gate electrode on the charge storage layer with a blocking insulation layer interposed therebetween, wherein a width of the second semiconductor pattern is greater than a width of the third semiconductor pattern.

Abstract translation: 非易失性存储器件包括：半导体引脚，包括第一半导体图案，第一半导体图案上的第二半导体图案和设置在第一半导体图案和第二半导体图案之间的第三半导体图案，将第一半导体图案和第二半导体图案 半导体图案，在第二半导体图案上的电荷存储层，其间插入有隧道绝缘层，以及在电荷存储层上的栅电极，其间插入有阻挡绝缘层，其中第二半导体图案的宽度大于宽度 的第三半导体图案。

公开(公告)号：US20050174910A1

公开(公告)日：2005-08-11

申请号：US11038085

申请日：2005-01-21

Applicant: Jong-Jin Lee

Inventor： Jong-Jin Lee

IPC: G11B7/00 ,  G11B7/085 ,  G11B7/09 ,  G11B15/18 ,  H02P8/22

CPC classification number: G11B7/08517 ,  G11B7/08505 ,  G11B7/08529

Abstract: There is provided a method for controlling a stepping motor by employing a micro-step mode at deceleration or acceleration of the stepping motor, which moves an optical pickup head in a full step mode or a half step mode, to minimize lens vibration of the optical pickup head. The method includes setting an initial step of the stepping motor, applying a micro-step mode to the stepping motor at the set initial step to move the optical pickup head, and after the initial step, applying a full step mode or a half step mode to the stepping motor to accelerate the optical pickup head by a desired speed. Also, the method includes setting a late step of the stepping motor, applying a full step mode or a half step mode to the stepping motor to decelerate the optical pickup head by a desired speed, and applying a micro-step mode to the stepping motor at the set late step to move the optical pickup head.

Abstract translation: 提供了一种通过在步进电机的减速或加速度下采用微步模式来控制步进电动机的方法，该步骤电动机以全步进模式或半步模式移动光学拾取头，以使光学器件的透镜振动最小化 拾音头。 该方法包括设置步进电机的初始步骤，在设定的初始步骤向步进电机施加微步模式以移动光学拾取头，并且在初始步骤之后，施加全步进模式或半步骤模式 到步进电机以以期望的速度加速光学拾取头。 此外，该方法包括设置步进电机的后期步骤，向步进电机施加全步进模式或半步模式以使光学拾取头减速所需速度，并将微步模式应用于步进电机 在设定的后期步骤移动光学头。

公开(公告)号：US20050095862A1

公开(公告)日：2005-05-05

申请号：US11003737

申请日：2004-12-06

Applicant: Jong-Jin Lee ,  Young-Hwan Shin

Inventor： Jong-Jin Lee ,  Young-Hwan Shin

IPC: C25D7/12 ,  C25D5/02 ,  C25D5/10 ,  H01L21/48 ,  H01L23/12 ,  H01L23/28 ,  H05K3/10 ,  H05K3/24 ,  H05K3/42 ,  H05K1/16

CPC classification number: H01L21/4846 ,  H01L21/4857 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/108 ,  H05K3/243 ,  H05K3/426 ,  H05K2203/1476 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package substrate manufactured by electrolytically plating Au in a semi-additive manner without using any plating lead line on wire bonding pads and solder ball pads, and a method for manufacturing the package substrate. The method includes the steps of forming a first copper plated layer on a base substrate having through holes and inner surfaces of the through holes, coating a first resist over the first copper plated layer, partially removing the first resist, thereby exposing portions of the first copper plated layer respectively corresponding to regions where circuit patterns are to be plated, forming a second copper plated layer on the exposed portions of the first copper plated layer, stripping the first resist, coating a second resist over the resultant structure, and removing the second resist from regions where wire bonding pads and solder ball pads are to be formed, removing exposed portions of the first copper plated layer, forming the wire bonding pads and the solder ball pads, removing the second resist, removing exposed portions of the first copper plated layer, and coating a solder resist over all surfaces of the resultant structure, and removing portions of the solder resist respectively covering the wire bonding pads and the solder ball pads.

Abstract translation: 通过以半添加方式对Au进行电镀而不使用引线接合焊盘和焊球垫上的任何电镀引线而制造的封装基板，以及制造封装基板的方法。 该方法包括以下步骤：在具有通孔和通孔的内表面的基底基板上形成第一镀铜层，在第一镀铜层上涂覆第一抗蚀剂，部分地除去第一抗蚀剂，从而暴露第一镀层 铜电镀层分别对应于要电镀图案的区域，在第一镀铜层的暴露部分上形成第二镀铜层，剥离第一抗蚀剂，在所得结构上涂覆第二抗蚀剂，并除去第二镀铜层 从要形成引线键合焊盘和焊球焊盘的区域抵抗，去除第一镀铜层的暴露部分，形成引线焊盘和焊球垫，去除第二抗蚀剂，去除第一镀铜层的暴露部分 并且在所得结构的所有表面上涂覆阻焊剂，并且分别去除阻焊部分 覆盖引线接合焊盘和焊球垫。

公开(公告)号：US20160293484A1

公开(公告)日：2016-10-06

申请号：US15000302

申请日：2016-01-19

Applicant: Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

Inventor： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

IPC: H01L21/768

CPC classification number: H01L21/76882 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

Abstract translation: 在形成布线结构的方法中，在基板上形成下部结构。 在下部结构上形成绝缘中间层。 部分去除绝缘中间层以形成至少一个通孔和虚拟通孔。 绝缘中间层的上部被部分地去除以形成连接通孔和虚拟通孔的沟槽。 形成填充通孔和虚拟通孔的第一金属层。 填充沟槽的第二金属层形成在第一金属层上。

公开(公告)号：US20160276267A1

公开(公告)日：2016-09-22

申请号：US15018484

申请日：2016-02-08

Applicant: Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Nae-In Lee ,  Jeong-Ok Cha ,  Jung-Ha Hwang

Inventor： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Nae-In Lee ,  Jeong-Ok Cha ,  Jung-Ha Hwang

IPC: H01L23/522 ,  H01L21/285 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53238

Abstract: Methods of forming wiring structures and methods of manufacturing semiconductor devices include forming a lower structure on a substrate, forming an interlayer insulating film including an opening on the lower structure, forming a liner film on an inner surface of the opening, treating a surface of the liner film by an ion bombardment, and forming a first conductive film on the liner film. The first conductive film is formed to be at least partially filled in the opening through a reflow process. Related wiring structures and semiconductor devices are also discussed.

Abstract translation: 形成布线结构的方法和制造半导体器件的方法包括在基板上形成下部结构，在下部结构上形成包括开口的层间绝缘膜，在开口的内表面上形成衬垫膜， 通过离子轰击形成衬垫膜，并在衬垫膜上形成第一导电膜。 第一导电膜通过回流工艺形成为至少部分地填充在开口中。 还讨论了相关的布线结构和半导体器件。

公开(公告)号：US07795719B2

公开(公告)日：2010-09-14

申请号：US12357643

申请日：2009-01-22

Applicant: Heung-Kyu Kim ,  Young-Hwan Shin ,  Jong-Jin Lee

Inventor： Heung-Kyu Kim ,  Young-Hwan Shin ,  Jong-Jin Lee

IPC: H01L23/02

CPC classification number: H01L23/5385 ,  H01L24/13 ,  H01L24/14 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/141 ,  H05K3/222 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: An electro component package is disclosed. The electro component package in accordance with an embodiment of the present invention includes a first package substrate having a first chip mounted on an upper surface thereof, the first chip having a through-via formed therein; a second package substrate being separated from the first package substrate and having a second chip mounted on an upper surface thereof; and a connection substrate having one end connected with an upper surface of the first chip and the other end connected with an upper surface of the second chip, the connection substrate electrically connecting the first chip with the second chip.

Abstract translation: 公开了电子部件封装。 根据本发明的实施例的电子部件封装包括：第一封装基板，其具有安装在其上表面上的第一芯片，所述第一芯片具有形成在其中的通孔; 第二封装衬底与第一封装衬底分离并且具有安装在其上表面上的第二芯片; 以及连接基板，其一端与所述第一芯片的上表面连接，所述另一端与所述第二芯片的上表面连接，所述连接基板将所述第一芯片与所述第二芯片电连接。

公开(公告)号：US07701162B2

公开(公告)日：2010-04-20

申请号：US11038085

申请日：2005-01-21

Applicant: Jong-Jin Lee

Inventor： Jong-Jin Lee

IPC: H02P8/00

CPC classification number: G11B7/08517 ,  G11B7/08505 ,  G11B7/08529

Abstract: There is provided a method for controlling a stepping motor by employing a micro-step mode at deceleration or acceleration of the stepping motor, which moves an optical pickup head in a full step mode or a half step mode, to minimize lens vibration of the optical pickup head. The method includes setting an initial step of the stepping motor, applying a micro-step mode to the stepping motor at the set initial step to move the optical pickup head, and after the initial step, applying a full step mode or a half step mode to the stepping motor to accelerate the optical pickup head by a desired speed. Also, the method includes setting a late step of the stepping motor, applying a full step mode or a half step mode to the stepping motor to decelerate the optical pickup head by a desired speed, and applying a micro-step mode to the stepping motor at the set late step to move the optical pickup head.

Abstract translation: 提供了一种通过在步进电机的减速或加速度下采用微步模式来控制步进电动机的方法，该步骤电动机以全步进模式或半步模式移动光学拾取头，以使光学器件的透镜振动最小化 拾音头。 该方法包括设置步进电机的初始步骤，在设定的初始步骤向步进电机施加微步模式以移动光学拾取头，并且在初始步骤之后，施加全步进模式或半步骤模式 到步进电机以以期望的速度加速光学拾取头。 此外，该方法包括设置步进电机的后期步骤，向步进电机施加全步进模式或半步模式以使光学拾取头减速所需速度，并将微步模式应用于步进电机 在设定的后期步骤移动光学头。

公开(公告)号：US07674661B2

公开(公告)日：2010-03-09

申请号：US11710488

申请日：2007-02-26

Applicant: Young-Joon Ahn ,  Suk-Pil Kim ,  Jong-Jin Lee

Inventor： Young-Joon Ahn ,  Suk-Pil Kim ,  Jong-Jin Lee

IPC: H01L21/00

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/4991 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/792

Abstract: In a memory device and a method of manufacturing the memory device, a pair of channel layers included in the memory device may be formed on a sidewall of the sacrificial single crystalline layer pattern located on a protrusion of a semiconductor substrate. Accordingly, an etch damage may be reduced at the channel layer. The sacrificial single crystalline layer pattern may be removed to generate a void between the pair of the channel layers. As a result, a generation of a coupling effect may be reduced between the channel layers.

Abstract translation: 在存储器件和存储器件的制造方法中，包括在存储器件中的一对沟道层可以形成在位于半导体衬底的突起上的牺牲单晶层图案的侧壁上。 因此，在沟道层可能会减少蚀刻损伤。 可以去除牺牲单晶层图案以在一对通道层之间产生空隙。 结果，可以在沟道层之间产生耦合效应。

公开(公告)号：US20090174799A1

公开(公告)日：2009-07-09

申请号：US12313350

申请日：2008-11-19

Applicant: Jong-Jin Lee ,  Ju-Hyun Ko ,  Jung-Chak Ahn

Inventor： Jong-Jin Lee ,  Ju-Hyun Ko ,  Jung-Chak Ahn

IPC: H04N5/335

CPC classification number: H04N5/361 ,  H01L27/14656 ,  H04N5/3594

Abstract: For driving an image sensor having a pixel with a transfer gate formed between a photo-detector and a floating diffusion region, a noise-reducing voltage is applied on the transfer gate during a first period of an integration mode. A blooming current voltage is applied on the transfer gate during a second period of the integration mode. A read voltage is applied on the transfer gate during a read mode after the integration mode. The read voltage has a higher magnitude than the blooming current voltage. With application of the noise-reducing voltage, noise is reduced and a dynamic range is extended for the image sensor.

Abstract translation: 为了驱动具有形成在光电检测器和浮动扩散区域之间的传输门的像素的图像传感器，在积分模式的第一周期期间，在传输门上施加降噪电压。 在积分模式的第二周期期间，在传输门上施加开花电流电压。 在积分模式之后的读取模式下，在传输门上施加读取电压。 读取电压的幅度比起霜电流电压高。 通过应用降噪电压，噪声降低，图像传感器的动态范围扩大。

公开(公告)号：US20080018757A1

公开(公告)日：2008-01-24

申请号：US11811630

申请日：2007-06-11

Applicant: Bum-Suk Kim ,  Alexander Getman ,  Jong-Jin Lee ,  Yun-Ho Jang ,  Jung-Chak Ahn

Inventor： Bum-Suk Kim ,  Alexander Getman ,  Jong-Jin Lee ,  Yun-Ho Jang ,  Jung-Chak Ahn

IPC: H04N3/14

CPC classification number: H04N9/045 ,  H04N2209/046

Abstract: For color correction in an image sensor, an image sensor processing block generates a plurality of color correction parameters corresponding to a plurality of selected pixels of the image sensor for defining a plurality of areas of a sample image. In addition, a color correction value calculation block generates a respective color correction value corresponding to a given pixel from bilinear interpolation of a respective subset of the color correction parameters corresponding to a respective one of the areas including a respective location of the given pixel.

Abstract translation: 对于图像传感器中的颜色校正，图像传感器处理块生成对应于图像传感器的多个选择像素的多个颜色校正参数，用于定义样本图像的多个区域。 此外，颜色校正值计算块根据对应于包括给定像素的相应位置的各个区域的颜色校正参数的相应子集的双线性插值，从给定像素生成对应于给定像素的相应颜色校正值。