公开(公告)号：US07432158B1

公开(公告)日：2008-10-07

申请号：US11459843

申请日：2006-07-25

申请人： Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

发明人： Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/36

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S977/774 ,  Y10S977/779 ,  Y10S977/78 ,  Y10S977/943

摘要： A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters is formed over the second portion. A layer of nitrided oxide is formed around each nanocluster of the first plurality and the second plurality of nanoclusters. Remote plasma nitridation is performed on the layers of nitrided oxide of the first plurality of nanoclusters. The nanoclusters are removed from the second portion. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

摘要翻译： 制造半导体器件的方法包括具有半导体层的衬底，该半导体层具有用于非易失性存储器的第一部分和不包括第一部分的第二部分。 第一介电层形成在半导体层上。 在第一部分上形成第一多个纳米团簇，并且在第二部分上形成第二多个纳米团簇。 在第一多个和第二多个纳米团簇的每个纳米簇周围形成氮化氧化物层。 在第一多个纳米团簇的氮化氧化物层上进行远程等离子体氮化。 从第二部分去除纳米团簇。 在半导体层上方形成第二电介质层。 在第二电介质层上形成导电层。

公开(公告)号：US20080199996A1

公开(公告)日：2008-08-21

申请号：US11676403

申请日：2007-02-19

申请人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

发明人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521

摘要： A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

摘要翻译： 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中在牺牲隔离物上形成的纳米团簇被去除并且其它纳米团簇保留。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。

公开(公告)号：US20080188052A1

公开(公告)日：2008-08-07

申请号：US11671809

申请日：2007-02-06

申请人： Brian A. Winstead ,  Taras A. Kirichenko ,  Konstantin V. Loiko ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Sung-Taeg Kang ,  Ko-Min Chang ,  Jane Yater

发明人： Brian A. Winstead ,  Taras A. Kirichenko ,  Konstantin V. Loiko ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Sung-Taeg Kang ,  Ko-Min Chang ,  Jane Yater

IPC分类号： H01L21/336

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7885

摘要： A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).

摘要翻译： 公开了一种半导体工艺和装置，用于通过在衬底（1）上的第一介电层（2）上形成选择栅极结构（3）来形成分裂栅极薄膜存储NVM器件（10）。 在具有嵌入的纳米晶体（15,16）的第二介电层（5）上形成控制栅极结构（6），使得所述控制栅极（6）与所述选择栅极结构（3）相邻，但是通过间隙（8 ）; 在形成在选择栅极结构和控制栅极结构之间的间隙（8）下面的衬底（1）中形成浮置掺杂区（4）; 以及在所述衬底中形成源/漏区（11,12）以限定包括所述浮置掺杂区（4）的沟道区。

公开(公告)号：US20080182428A1

公开(公告)日：2008-07-31

申请号：US11627817

申请日：2007-01-26

申请人： Tushar P. Merchant ,  Chun-Li Liu ,  Ramachandran Muralidhar ,  Marius K. Orlowski ,  Rajesh A. Rao ,  Matthew Stoker

发明人： Tushar P. Merchant ,  Chun-Li Liu ,  Ramachandran Muralidhar ,  Marius K. Orlowski ,  Rajesh A. Rao ,  Matthew Stoker

IPC分类号： H01L21/31

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/11524 ,  H01L29/7887 ,  Y10S977/932 ,  Y10S977/943

摘要： An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.

摘要翻译： 电子设备可以包括不连续的存储元件层。 覆盖不连续存储元件的电介质层可以是基本上无氢的。 形成电子器件的过程可以包括在不连续的存储元件上形成包括硅的层。 在一个实施方案中，该方法包括至少基本上氧化所有该层。 在另一个实施方案中，该方法包括使用基本上无氢的硅前体材料形成该层并至少基本上全部氧化。

公开(公告)号：US20080182377A1

公开(公告)日：2008-07-31

申请号：US11668210

申请日：2007-01-29

申请人： Rajesh A. Rao ,  Ramachandran Muralidhar

发明人： Rajesh A. Rao ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/66772 ,  H01L29/7887

摘要： In making a multi-bit memory cell, a first insulating layer is formed over a semiconductor substrate. A second insulating layer is formed over the first insulating layer. A layer of gate material is formed over the second insulating layer and patterned to leave a gate portion. The second insulating layer is etched to undercut the gate portion and leave a portion of the second insulating layer between the first insulating layer and the gate portion. Nanocrystals are formed on the first insulating layer. A first portion of the nanocrystals is under the gate portion on a first side of the portion of the second insulating layer and a second portion of the nanocrystals is under the gate portion on a second side of the portion of the second insulating layer. The first and second portions of the nanocrystals are for storing logic states of first and second bits, respectively.

摘要翻译： 在制造多位存储单元时，在半导体衬底上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 一层栅极材料形成在第二绝缘层之上并图案化以留下栅极部分。 蚀刻第二绝缘层以切割栅极部分，并将第二绝缘层的一部分留在第一绝缘层和栅极部分之间。 在第一绝缘层上形成纳米晶体。 纳米晶体的第一部分在第二绝缘层部分的第一侧上的栅极部分下方，并且纳米晶体的第二部分在第二绝缘层部分的第二侧上的栅极部分下方。 纳米晶体的第一和第二部分分别用于存储第一和第二位的逻辑状态。

公开(公告)号：US20080121966A1

公开(公告)日：2008-05-29

申请号：US11530053

申请日：2006-09-08

申请人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

发明人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/7881 ,  Y10S977/773

摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

公开(公告)号：US06991984B2

公开(公告)日：2006-01-31

申请号：US10765804

申请日：2004-01-27

申请人： Paul A. Ingersoll ,  Gowrishankar L. Chindalore ,  Ramachandran Muralidhar

发明人： Paul A. Ingersoll ,  Gowrishankar L. Chindalore ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4925 ,  H01L29/4958

摘要： To increase the gate coupling ratio of a semiconductor device 10, discrete elements 22, such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements 22 are pre-formed in a vapor phase and are attached to the semiconductor device 10 by electrostatic force. In one embodiment, the discrete elements 22 are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer 17 may be formed between the floating gate 16 and the discrete elements 22.

摘要翻译： 为了增加半导体器件10的栅极耦合比，离散元件22（例如纳米晶体）沉积在浮动栅极16上。 在一个实施例中，分立元件22预先形成为气相并且通过静电力附着到半导体器件10。 在一个实施例中，分立元件22预先形成在不同于它们附接的腔室的腔室中。 在另一个实施例中，相同的室用于整个沉积工艺。 可选的界面层17可以形成在浮动栅极16和离散元件22之间。

公开(公告)号：US06808986B2

公开(公告)日：2004-10-26

申请号：US10231556

申请日：2002-08-30

申请人： Rajesh A. Rao ,  Ramachandran Muralidhar ,  Tushar P. Merchant

发明人： Rajesh A. Rao ,  Ramachandran Muralidhar ,  Tushar P. Merchant

IPC分类号： H01L21336

CPC分类号： B82Y10/00 ,  C23C16/02 ,  C23C16/24 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/0262 ,  H01L21/28273 ,  H01L29/42332

摘要： Nanocrystals (22) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric (18) overlies a substrate (12) and is placed in a chemical vapor deposition chamber (34). A first precursor gas, such as disilane (36), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals (22) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.

公开(公告)号：US06297095B1

公开(公告)日：2001-10-02

申请号：US09596399

申请日：2000-06-16

申请人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

发明人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

IPC分类号： H01L21336

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/66439 ,  H01L29/7888

摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).

摘要翻译： 提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。 该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。 然后在隧道介电层（14）上生长多个纳米团簇（19）。 在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。 为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。 然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。 在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间 电极（24）。

公开(公告)号：US08895384B2

公开(公告)日：2014-11-25

申请号：US13293210

申请日：2011-11-10

申请人： Unoh Kwon ,  Ramachandran Muralidhar ,  Viorel Ontalus

发明人： Unoh Kwon ,  Ramachandran Muralidhar ,  Viorel Ontalus

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364

摘要： A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.

摘要翻译： 提供了具有通道材料的金属栅极结构及其制造方法。 该方法包括在衬底上形成虚拟栅极结构。 该方法还包括在虚拟栅极结构的侧壁上形成侧壁结构。 该方法还包括去除伪栅极结构以形成由侧壁结构限定的第一沟槽和第二沟槽。 该方法还包括在第一沟槽和第二沟槽中的衬底上形成沟道材料。 该方法还包括在第一沟槽被掩蔽的同时从第二沟槽去除沟道材料。 该方法还包括用栅极材料填充第一沟槽和第二沟槽的剩余部分。