Architecture of ballast with integrated RF interface
    31.
    发明授权
    Architecture of ballast with integrated RF interface 失效
    具有集成射频接口的镇流器结构

    公开(公告)号:US06636005B2

    公开(公告)日:2003-10-21

    申请号:US09991082

    申请日:2001-11-14

    IPC分类号: G05F100

    CPC分类号: H05B37/0272 Y10S315/04

    摘要: The invention is a new architecture for a high frequency (HF) ballast with wireless communication interface. The new architecture integrates the RF wireless interface into the ballast. A user control transmits an RF control signal to a second antenna at the ballast site which provides the RF signal to the ballast which activates the fluorescent lamp. The ballast includes a transceiver/receiver, a communication decoder, a power control stage and a power stage. The transceiver/receiver receives the RF signal and communicates it to the communication decoder which acts as an interface to the power stage control. The power stage control controls the power stage that activates the fluorescent lamp. The communication decoder, power control stage, power stage and transceiver/receiver are located within the ballast enclosure which is an important part of the invention. If the power stage control is digital it may be combined with the communication decoder into one microprocessor or digital controller such as an ASIC. The communication decoder may be a serial interface. The transceiver/receiver is an RF integrated circuit. The ballast further includes an isolator to isolate the transceiver/receiver from the first antenna. The isolator may be capacitive.

    摘要翻译: 本发明是具有无线通信接口的高频(HF)镇流器的新架构。 新架构将RF无线接口集成到镇流器中。 用户控制将RF控制信号发送到镇流器站点处的第二天线,该第二天线将RF信号提供给激活荧光灯的镇流器。 镇流器包括收发器/接收器,通信解码器,功率控制级和功率级。 收发器/接收器接收RF信号并将其传送到作为功率级控制的接口的通信解码器。 功率级控制器控制激活荧光灯的功率级。 通信解码器,功率控制级,功率级和收发器/接收器位于镇流器外壳内,这是本发明的重要部分。 如果功率级控制是数字的,则它可以与通信解码器组合成一个微处理器或诸如ASIC的数字控制器。 通信解码器可以是串行接口。 收发器/接收器是RF集成电路。 镇流器还包括隔离器,以将收发器/接收器与第一天线隔离。 隔离器可以是电容的。

    Methods for gene expression monitoring on electronic microarrays
    32.
    发明授权
    Methods for gene expression monitoring on electronic microarrays 有权
    电子微阵列基因表达监测方法

    公开(公告)号:US06379897B1

    公开(公告)日:2002-04-30

    申请号:US09710200

    申请日:2000-11-09

    IPC分类号: C12Q168

    摘要: The present invention presents methods for gene expression monitoring that utilize microelectronic arrays to drive the transport and hybridization of nucleic acids. Procedures are described for generating mRNA expression samples for use in these methods from populations of cells, tissues, or other biological source materials, that may differ in their physiological and/or pathological state. Provided in the invention are methods for generating a reusable nucleic acid transcript library from mRNA in a sample of biological material. In order to improve gene expression monitoring on the microelectronic arrays, the transcripts are amplified to produce sample nucleic acid amplicons of a defined length. Because multiple sample amplicons may be selectively hybridized to controlled sites in the electronic array, the gene expression profiles of the polynucleotide populations from different sources can be directly compared in an array format using electronic hybridization methodologies. Also provided in the invention are methods for detecting the level of sample amplicons using electronically assisted primer extension detection, and utilizing individual test site hybridization controls. The hybridization data collected utilizing the improved methods of the present invention will allow the correlation of changes in mRNA level with the corresponding expression of the encoded protein in the biological source material, and thus aid in studying the role of gene expression in disease.

    摘要翻译: 本发明提出了利用微电子阵列驱动核酸转运和杂交的基因表达监测方法。 描述了用于从细胞,组织或其他生物来源材料的群体中产生用于这些方法的mRNA表达样品的程序,其可能在其生理和/或病理状态方面不同。 本发明提供了用于从生物材料样品中的mRNA产生可重复使用的核酸转录本文库的方法。 为了改善微电子阵列上的基因表达监测,扩增转录物以产生具有确定长度的样品核酸扩增子。 因为多个样品扩增子可以选择性地杂交到电子阵列中的受控位点,所以可以使用电子杂交方法以阵列格式直接比较来自不同来源的多核苷酸群体的基因表达谱。 本发明还提供了使用电子辅助引物延伸检测和利用单独的测试位点杂交控制来检测样品扩增子水平的方法。 使用本发明改进方法收集的杂交数据将允许mRNA水平的变化与生物来源材料中编码的蛋白质的相应表达的相关性,从而有助于研究基因表达在疾病中的作用。

    Disc drive having gram load reducer and method of operating gram load
reducer
    33.
    发明授权
    Disc drive having gram load reducer and method of operating gram load reducer 失效
    具有克负载减速器的盘式驱动器和操作克减速器的方法

    公开(公告)号:US5991114A

    公开(公告)日:1999-11-23

    申请号:US855678

    申请日:1997-05-14

    摘要: An actuator assembly in a disc drive includes a track accessing arm, a load beam and a slider. A proximal end of the load beam is mounted to the track accessing arm and a distal end of the load beam carries the slider proximate to a rotatable data storage disc. The load beam transmits a load force to the slider in the direction of the data storage disc. A support beam extends from the track accessing arm and supports a load force reducer between the support arm and the load beam. The load force reducer is operatively coupled between the support beam and the load beam for reducing the load force during take-off and landing of the slider relative to the disc surface.

    摘要翻译: 盘驱动器中的致动器组件包括轨道接近臂,负载梁和滑块。 负载梁的近端安装到轨道接近臂,并且负载梁的远端将滑块接近靠近可旋转的数据存储盘。 负载梁在数据存储盘的方向上向滑块传递负载力。 支撑梁从轨道接近臂延伸并且在支撑臂和负载梁之间支撑负载力减小器。 负载力减速器可操作地联接在支撑梁和负载梁之间,用于减小滑块相对于盘表面的起飞和着陆期间的负载力。

    Reconfigurable circuit and decoder therefor
    34.
    发明授权
    Reconfigurable circuit and decoder therefor 有权
    可重构电路及解码器

    公开(公告)号:US09110133B2

    公开(公告)日:2015-08-18

    申请号:US14277053

    申请日:2014-05-14

    摘要: A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.

    摘要翻译: 在可重构电路中用于解码数字脉冲的数字解码器包括具有耦合到参考脉冲输入和数据脉冲输入的输入的相位指示器模块。 相位指示器模块具有提供指示在参考脉冲输入和数据脉冲输入上出现的脉冲的上升沿和下降沿的逻辑值的定时信息输出。 相位解码器模块具有耦合到定时信息输出的输入,并且输出解码的二进制数据值。 在操作中,相位解码器模块将定时信息输出处的至少两个逻辑值与施加到相位输入之一的脉冲的代表性的前沿和后沿的信号进行比较,以确定相位输入上的脉冲到达顺序序列, 从而提供解码的二进制数据值。

    Serializer with multiple stages
    35.
    发明授权
    Serializer with multiple stages 有权
    具有多个阶段的串行器

    公开(公告)号:US08912933B1

    公开(公告)日:2014-12-16

    申请号:US13616173

    申请日:2012-09-14

    IPC分类号: H03M9/00

    CPC分类号: H03M9/00

    摘要: In certain embodiments of the invention, a serializer has a transfer stage that transfers N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain and a serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that buffers the data and can be used to toggle the serializer between an N−1 operating mode and an N+1 operating mode.

    摘要翻译: 在本发明的某些实施例中,串行器具有将N位并行数据从相对较慢的定时域传送到相对较快的定时域的传送级,以及将并行数据转换成串行数据的串行级。 在传送级和序列化级之间是缓存数据并可用于在N-1操作模式和N + 1操作模式之间切换串行器的更新阶段。

    Bandgap circuit having a zero temperature coefficient
    37.
    发明授权
    Bandgap circuit having a zero temperature coefficient 有权
    具有零温度系数的带隙电路

    公开(公告)号:US08179115B2

    公开(公告)日:2012-05-15

    申请号:US12503819

    申请日:2009-07-15

    申请人: Ling Wang

    发明人: Ling Wang

    IPC分类号: G05F3/16 G05F1/40

    CPC分类号: G05F3/30

    摘要: A bandgap circuit is provided, which includes a current source, a voltage boost circuit, a voltage input circuit, a voltage equalizer circuit, and a voltage output circuit. The current source provides a first current, a second current, and a third current, which are equal to one another. The voltage boost circuit provides a boost voltage by a single current path. The voltage input circuit receives the first and the second currents, and provides a first input voltage and a second input voltage based on the boost voltage. The voltage equalizer circuit receives the first and the second input voltages and equalize the two input voltages. The voltage output circuit provides a bandgap reference voltage according to the third current.

    摘要翻译: 提供了带隙电路,其包括电流源,升压电路,电压输入电路,电压均衡器电路和电压输出电路。 电流源提供彼此相等的第一电流,第二电流和第三电流。 升压电路通过单个电流路径提供升压电压。 电压输入电路接收第一和第二电流,并且基于升压提供第一输入电压和第二输入电压。 电压均衡器电路接收第一和第二输入电压并均衡两个输入电压。 电压输出电路根据第三电流提供带隙基准电压。

    Entity-based business intelligence
    39.
    发明授权
    Entity-based business intelligence 有权
    基于实体的商业智能

    公开(公告)号:US07979436B2

    公开(公告)日:2011-07-12

    申请号:US12133552

    申请日:2008-06-05

    IPC分类号: G06F7/00

    CPC分类号: G06F17/30592 G06F17/30489

    摘要: A method is disclosed for conducting a query to transform data in a pre-existing database, the method comprising: collecting database information from the pre-existing database, the database information including inconsistent dimensional tables and fact tables; running an entity discovery process on the inconsistent dimensional tables and the fact tables to produce entity mapping tables; using the entity mapping tables to resolve the inconsistent dimensional tables into resolved dimensional tables; and running the query on a resolved database to obtain a query result, the resolved database including the resolved dimensional table.

    摘要翻译: 公开了一种用于进行在预先存在的数据库中转换数据的查询的方法,所述方法包括:从预先存在的数据库收集数据库信息,所述数据库信息包括不一致的维度表和事实表; 对不一致的维度表和事实表运行实体发现过程以生成实体映射表; 使用实体映射表将不一致的维度表解析为已解析的维度表; 并在解析的数据库上运行查询以获取查询结果,解析的数据库包括已解析的维度表。