公开(公告)号：US20100277986A1

公开(公告)日：2010-11-04

申请号：US12432214

申请日：2009-04-29

申请人： Chih-Wei Hung ,  Chia-Ta Hsieh ,  Luan C. Tran

发明人： Chih-Wei Hung ,  Chia-Ta Hsieh ,  Luan C. Tran

IPC分类号： G11C16/06 ,  H03K19/177 ,  G11C7/00

CPC分类号： G11C16/10 ,  G11C16/0441 ,  H03K19/1776

摘要： A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful.

摘要翻译： 非易失性存储器件包括耦合到位线和字线的第一金属氧化物半导体（CMOS）器件和耦合到第一CMOS器件的第二CMOS器件。 第二CMOS器件还耦合到互补位线和互补字线。 第一和第二CMOS器件彼此互补。 输出节点耦合在第一CMOS器件和第二CMOS器件之间。 编程非易失性现场可编程门阵列（NV-FPGA）的方法包括将信息处理系统耦合到FPGA，对FPGA中的多个存储单元进行块擦除，验证块擦除成功，编程 FPGA的上一页，验证上页编程是否成功，编写FPGA的下一页，并验证下页编程是否成功。

公开(公告)号：US07776683B2

公开(公告)日：2010-08-17

申请号：US12119831

申请日：2008-05-13

申请人： Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

发明人： Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

IPC分类号： H01L21/8242

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

摘要翻译： 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形末端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

公开(公告)号：US07648919B2

公开(公告)日：2010-01-19

申请号：US11407429

申请日：2006-04-20

申请人： Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

发明人： Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

公开(公告)号：US07611944B2

公开(公告)日：2009-11-03

申请号：US11216477

申请日：2005-08-31

申请人： Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

发明人： Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

IPC分类号： H01L21/8242

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

摘要翻译： 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

公开(公告)号：US20090152645A1

公开(公告)日：2009-06-18

申请号：US11959409

申请日：2007-12-18

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L21/308

CPC分类号： H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

摘要： Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

摘要翻译： 半导体材料的连续环路的不同部分彼此电隔离。 在一些实施例中，环路的端部与环路的中间部分电隔离。 在一些实施例中，具有在其端部连接在一起的两个腿的半导体材料的环通过间距倍增过程形成，其中间隔物的环形成在心轴的侧壁上。 去除心轴并且将一块掩模材料覆盖在间隔环的至少一端上。 在一些实施例中，掩模材料块覆盖间隔环的每一端。 由间隔物和块限定的图案被转移到半导体材料层。 这些块将所有环路电连接在一起。 沿循环的每条腿形成选择门。 这些块作为源/排水沟。 选择门被偏置在关闭状态以防止电流从环路的中部流向块，从而将中间部分与环的端部电隔离，并且还将环路的不同的腿与每个 其他。

公开(公告)号：US07547604B2

公开(公告)日：2009-06-16

申请号：US11730717

申请日：2007-04-03

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/336

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10891 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

摘要： Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

摘要翻译： 公开了自对准凹陷门结构和形成方法。 首先在半导体衬底中形成用于隔离的场氧化物区域。 多个列限定在形成在半导体衬底上的绝缘层中，接着在半导体衬底的暴露区域上形成薄的牺牲氧化物层，但不在场氧化物区域上。 然后在每列的侧壁和牺牲氧化物层和场氧化物区域的部分上方提供电介质材料。 进行第一蚀刻以在半导体衬底内形成第一组沟槽和在场氧化物区域内形成多个凹陷。 进行第二蚀刻以去除残留在柱的侧壁上的电介质残余物并形成第二组沟槽。 然后将多晶硅沉积在第二组沟槽内并在凹槽内形成凹陷的导电栅极。

公开(公告)号：US20090032963A1

公开(公告)日：2009-02-05

申请号：US11833386

申请日：2007-08-03

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L23/48 ,  H01L21/311 ,  H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L27/108 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

摘要翻译： 制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。 还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。

公开(公告)号：US07405455B2

公开(公告)日：2008-07-29

申请号：US11126455

申请日：2005-05-10

申请人： Leonard Forbes ,  Kie Y. Ahn ,  Luan C. Tran

发明人： Leonard Forbes ,  Kie Y. Ahn ,  Luan C. Tran

IPC分类号： H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28273 ,  H01L29/4941 ,  H01L29/6656

摘要： One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layered-defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.

摘要翻译： 本发明的一个方面包括形成半导体结构的方法。 形成图案线以包括第一层和第二层。 第一层包括硅，第二层包括金属。 线具有包括第一层限定部分和第二层限定部分的至少一个侧壁边缘。 沿着至少一个侧壁边缘形成第三层。 第三层包括硅并沿着侧壁边缘的第一层限定部分和侧壁边缘的第二层限定部分。 第三层的硅与第二层的金属反应，沿着侧壁边缘的第二层限定部分形成硅化物。 去除第三层的硅以留下第一层的硅，第二层的金属和硅化物。

公开(公告)号：US07378311B2

公开(公告)日：2008-05-27

申请号：US10929046

申请日：2004-08-27

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/8239 ,  H01L21/8242

CPC分类号： H01L27/10873 ,  H01L27/0214 ,  H01L27/10894 ,  Y10S257/906 ,  Y10S438/981

摘要： The invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.

摘要翻译： 本发明包括形成在半导体衬底上的6F 2 DRAM阵列。 存储器阵列包括第一存储单元。 第一存储单元包括第一存取晶体管和第一数据存储电容器。 第一存取晶体管的第一负载电极经由形成在衬底上的第一存储节点耦合到第一数据存储电容器。 存储器阵列还包括第二存储器单元。 第二存储单元包括第二存取晶体管和第二数据存储电容器。 第二存取晶体管的第一负载电极经由形成在基板上的第二存储节点耦合到第二数据存储电容器。 第一和第二存取晶体管具有具有第一厚度的栅极电介质。 存储器阵列还包括形成在第一和第二存储节点之间并被配置为在它们之间提供电隔离的隔离栅极。 隔离栅极具有第二厚度大于第一厚度的栅极电介质。 隔离栅极电介质可以在衬底的表面上方或下方延伸。

公开(公告)号：US06806123B2

公开(公告)日：2004-10-19

申请号：US10133193

申请日：2002-04-26

申请人： Mark McQueen ,  Luan C. Tran ,  Chandra Mouli

发明人： Mark McQueen ,  Luan C. Tran ,  Chandra Mouli

IPC分类号： H01L21332

CPC分类号： H01L27/10873 ,  H01L21/28123 ,  H01L27/105 ,  H01L27/10882 ,  H01L27/10894

摘要： The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×1017 atoms/cm3 with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

摘要翻译： 本发明包括其中具有结构的DRAM阵列，其包括通过中间绝缘材料与第二材料分离的第一材料。 第一种材料与n型和p型掺杂剂掺杂至至少1×10 17个原子/ cm 3。 本发明还包括半导体结构，其中掺杂材料在衬底的一段上方。 掺杂材料在其中具有第一类型多数掺杂剂，并且与电接地电连接。 一对导电掺杂的扩散区域与该段相邻，并且通过该段的至少一部分彼此间隔开。 导电掺杂扩散区域中具有第二类型多数掺杂剂。 本发明还包括形成半导体结构的方法。